Mark Bauer

Person

Cameron Park, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Block-level read while write method and apparatus
- Patent number 6,772,273
- Issue date Aug 3, 2004
- Intel Corporation
- Kerry D. Tedrow
- G11 - INFORMATION STORAGE
Information Patent Grant
Kicker for non-volatile memory drain bias
- Patent number 6,744,671
- Issue date Jun 1, 2004
- Intel Corporation
- Ritesh Trivedi
- G11 - INFORMATION STORAGE
Information Patent Grant
Load for non-volatile memory drain bias
- Patent number 6,570,789
- Issue date May 27, 2003
- Intel Corporation
- Ritesh Trivedi
- G11 - INFORMATION STORAGE
Information Patent Grant
Drain bias for non-volatile memory
- Patent number 6,535,423
- Issue date Mar 18, 2003
- Intel Corporation
- Ritesh Trivedi
- G11 - INFORMATION STORAGE
Information Patent Grant
Bit map addressing schemes for flash memory
- Patent number 6,483,742
- Issue date Nov 19, 2002
- Intel Corporation
- Sherif Sweha
- G11 - INFORMATION STORAGE
Information Patent Grant
Local sensing of non-volatile memory
- Patent number 6,477,086
- Issue date Nov 5, 2002
- Intel Corporation
- Ritesh Trivedi
- G11 - INFORMATION STORAGE
Information Patent Grant
Sample and hold voltage reference source
- Patent number 6,434,049
- Issue date Aug 13, 2002
- Intel Corporation
- Ritesh Trivedi
- G11 - INFORMATION STORAGE
Information Patent Grant
Dynamic single bit per cell to multiple bit per cell memory
- Patent number 6,097,637
- Issue date Aug 1, 2000
- Intel Corporation
- Mark E. Bauer
- G11 - INFORMATION STORAGE
Information Patent Grant
Sensing scheme for flash memory with multilevel cells
- Patent number 5,828,616
- Issue date Oct 27, 1998
- Intel Corporation
- Mark E. Bauer
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and circuitry for usage of partially functional nonvolatile...
- Patent number 5,822,256
- Issue date Oct 13, 1998
- Intel Corporation
- Mark E. Bauer
- G11 - INFORMATION STORAGE
Information Patent Grant
Bit map addressing schemes for flash memory
- Patent number 5,815,443
- Issue date Sep 29, 1998
- Intel Corporation
- Sherif Sweha
- G11 - INFORMATION STORAGE
Information Patent Grant
Deselected word line that floats during MLC programming of a flash...
- Patent number 5,801,991
- Issue date Sep 1, 1998
- Intel Corporation
- Stephen N. Keeney
- G11 - INFORMATION STORAGE
Information Patent Grant
Bit map addressing schemes for flash memory
- Patent number 5,796,667
- Issue date Aug 18, 1998
- Intel Corporation
- Sherif Sweha
- G11 - INFORMATION STORAGE
Information Patent Grant
Bit map addressing schemes for flash/memory
- Patent number 5,781,472
- Issue date Jul 14, 1998
- Intel Corporation
- Sherif Sweha
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for correcting a multilevel cell memory by usi...
- Patent number 5,754,566
- Issue date May 19, 1998
- Intel Corporation
- Mark J. Christopherson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Sensing scheme for flash memory with multilevel cells
- Patent number 5,748,546
- Issue date May 5, 1998
- Intel Corporation
- Mark E. Bauer
- G11 - INFORMATION STORAGE
Information Patent Grant
Nonvolatile memory blocking architecture
- Patent number 5,663,923
- Issue date Sep 2, 1997
- Intel Corporation
- Robert L. Baltar
- G11 - INFORMATION STORAGE
Information Patent Grant
Write verify schemes for flash memory with multilevel cells
- Patent number 5,539,690
- Issue date Jul 23, 1996
- Intel Corporation
- Sanjay S. Talreja
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for verifying the programming of multi-level f...
- Patent number 5,523,972
- Issue date Jun 4, 1996
- Intel Corporation
- Mamun Rashid
- G11 - INFORMATION STORAGE
Information Patent Grant
Dual row selection using multiplexed tri-level decoder
- Patent number 5,517,138
- Issue date May 14, 1996
- Intel Corporation
- Robert L. Baltar
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for sensing the state of floating gate memory...
- Patent number 5,508,958
- Issue date Apr 16, 1996
- Intel Corporation
- Albert Fazio
- G11 - INFORMATION STORAGE
Information Patent Grant
Bit map addressing schemes for flash memory
- Patent number 5,497,354
- Issue date Mar 5, 1996
- Intel Corporation
- Sherif Sweha
- G11 - INFORMATION STORAGE
Information Patent Grant
Drain bias multiplexing for multiple bit flash cell
- Patent number 5,485,422
- Issue date Jan 16, 1996
- Intel Corporation
- Mark E. Bauer
- G11 - INFORMATION STORAGE
Information Patent Grant
Error management processes for flash EEPROM memory arrays
- Patent number 5,475,693
- Issue date Dec 12, 1995
- Intel Corporation
- Mark Christopherson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus for fast internal reference cell trimming
- Patent number 5,444,656
- Issue date Aug 22, 1995
- Intel Corporation
- Mark Bauer
- G11 - INFORMATION STORAGE
Information Patent Grant
Programmable redundancy scheme suitable for single-bit state and mu...
- Patent number 5,438,546
- Issue date Aug 1, 1995
- Intel Corporation
- Michel I. Ishac
- G11 - INFORMATION STORAGE
Information Patent Grant
Sense amplifiers and sensing methods
- Patent number 5,394,037
- Issue date Feb 28, 1995
- Lattice Semiconductor Corporation
- Gregg R. Josephson
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
High-speed tri-level decoder with dual-voltage isolation
- Patent number 5,274,278
- Issue date Dec 28, 1993
- Intel Corporation
- Mark E. Bauer
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
Load for non-volatile memory drain bias
- Publication number 20020126527
- Publication date Sep 12, 2002
- Ritesh Trivedi
- G11 - INFORMATION STORAGE
Information Patent Application
Local sensing of non-volatile memory
- Publication number 20020085424
- Publication date Jul 4, 2002
- Ritesh Trivedi
- G11 - INFORMATION STORAGE
Information Patent Application
SAMPLE AND HOLD VOLTAGE REFERENCE SOURCE
- Publication number 20020085413
- Publication date Jul 4, 2002
- Ritesh Trivedi
- G11 - INFORMATION STORAGE
Information Patent Application
Drain bias for non-volatile memory
- Publication number 20020085421
- Publication date Jul 4, 2002
- Ritesh Trivedi
- G11 - INFORMATION STORAGE
Information Patent Application
Drain bias for non-volatile memory
- Publication number 20020085422
- Publication date Jul 4, 2002
- Ritesh Trivedi
- G11 - INFORMATION STORAGE

Person

Patents Grantslast 30 patents

Block-level read while write method and apparatus

Kicker for non-volatile memory drain bias

Load for non-volatile memory drain bias

Drain bias for non-volatile memory

Bit map addressing schemes for flash memory

Local sensing of non-volatile memory

Sample and hold voltage reference source

Dynamic single bit per cell to multiple bit per cell memory

Sensing scheme for flash memory with multilevel cells

Method and circuitry for usage of partially functional nonvolatile...

Bit map addressing schemes for flash memory

Deselected word line that floats during MLC programming of a flash...

Bit map addressing schemes for flash memory

Bit map addressing schemes for flash/memory

Method and apparatus for correcting a multilevel cell memory by usi...

Sensing scheme for flash memory with multilevel cells

Nonvolatile memory blocking architecture

Write verify schemes for flash memory with multilevel cells

Method and apparatus for verifying the programming of multi-level f...

Dual row selection using multiplexed tri-level decoder

Method and apparatus for sensing the state of floating gate memory...

Bit map addressing schemes for flash memory

Drain bias multiplexing for multiple bit flash cell

Error management processes for flash EEPROM memory arrays

Apparatus for fast internal reference cell trimming

Programmable redundancy scheme suitable for single-bit state and mu...

Sense amplifiers and sensing methods

High-speed tri-level decoder with dual-voltage isolation

Patents Applicationslast 30 patents

Load for non-volatile memory drain bias

Local sensing of non-volatile memory

SAMPLE AND HOLD VOLTAGE REFERENCE SOURCE

Drain bias for non-volatile memory

Drain bias for non-volatile memory