Mark Hoinkis

Person

East Fishkill, NY, US

People

Patents Grantslast 30 patents

Information Patent Grant
Methods for etching a metal layer to form an interconnection struct...
- Patent number 9,960,052
- Issue date May 1, 2018
- Applied Materials, Inc.
- Sumit Agarwal
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Selective sputtering for pattern transfer
- Patent number 9,493,879
- Issue date Nov 15, 2016
- Applied Materials, Inc.
- Mark Hoinkis
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Grant
Sputter etch processing for heavy metal patterning in integrated ci...
- Patent number 9,484,220
- Issue date Nov 1, 2016
- International Business Machines Corporation
- Mark D. Hoinkis
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Sidewall image transfer for heavy metal patterning in integrated ci...
- Patent number 9,171,796
- Issue date Oct 27, 2015
- International Business Machines Corporation
- Markus Brink
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Copper residue chamber clean
- Patent number 9,114,438
- Issue date Aug 25, 2015
- Applied Materials, Inc.
- Mark Hoinkis
- B08 - CLEANING
Information Patent Grant
Subtractive plasma etching of a blanket layer of metal or metal alloy
- Patent number 8,871,107
- Issue date Oct 28, 2014
- International Business Machines Corporation
- Nicholas C. M. Fuller
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and apparatus of stress relief in semiconductor structures
- Patent number 7,786,007
- Issue date Aug 31, 2010
- Infineon Technologies AG
- Mark Hoinkis
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Back end interconnect with a shaped interface
- Patent number 7,494,915
- Issue date Feb 24, 2009
- International Business Machines Corporation
- Lawrence A. Clevenger
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and apparatus of stress relief in semiconductor structures
- Patent number 7,368,804
- Issue date May 6, 2008
- Infineon Technologies AG
- Mark Hoinkis
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Bilayered metal hardmasks for use in dual damascene etch schemes
- Patent number 7,241,681
- Issue date Jul 10, 2007
- Infineon Technologies AG
- Kaushik Kumar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for depositing a metal layer on a semiconductor interconnect...
- Patent number 7,241,696
- Issue date Jul 10, 2007
- International Business Machines Corporation
- Larry Clevenger
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Back end interconnect with a shaped interface
- Patent number 7,122,462
- Issue date Oct 17, 2006
- International Business Machines Corporation
- Lawrence A. Clevenger
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Dual damascene structure and method
- Patent number 7,091,612
- Issue date Aug 15, 2006
- Infineon Technologies AG
- Kaushik Kumar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Reduction of the shear stress in copper via's in organic interlayer...
- Patent number 7,060,619
- Issue date Jun 13, 2006
- Infineon Technologies AG
- Andy Cowley
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Bilayered metal hardmasks for use in Dual Damascene etch schemes
- Patent number 7,052,621
- Issue date May 30, 2006
- Infineon Technologies AG
- Kaushik Kumar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Crystallographic modification of hard mask properties
- Patent number 7,001,835
- Issue date Feb 21, 2006
- International Business Machines Corporation
- Lawrence A. Clevenger
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Stress-relief layer for semiconductor applications
- Patent number 6,960,835
- Issue date Nov 1, 2005
- Infineon Technologies AG
- Hans-Joachim Barth
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Device interconnection
- Patent number 6,870,263
- Issue date Mar 22, 2005
- Infineon Technologies AG
- Lawrence A. Clevenger
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Via density rules
- Patent number 6,864,171
- Issue date Mar 8, 2005
- Infineon Technologies AG
- Mark D. Hoinkis
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Chromium adhesion layer for copper vias in low-k technology
- Patent number 6,539,625
- Issue date Apr 1, 2003
- International Business Machines Corporation
- Brett H. Engel
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Copper vias in low-k technology
- Patent number 6,383,929
- Issue date May 7, 2002
- International Business Machines Corporation
- Steven H. Boettcher
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Vertical fuse and method of fabrication
- Patent number 6,242,789
- Issue date Jun 5, 2001
- Infineon Technologies North America Corp.
- Stefan J. Weber
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of making a microelectronic structure
- Patent number 6,221,757
- Issue date Apr 24, 2001
- Infineon Technologies AG
- Sven Schmidbauer
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Tungsten-filled deep trenches
- Patent number 6,218,298
- Issue date Apr 17, 2001
- Infineon Technologies North America Corp.
- Mark D. Hoinkis
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Grant
Vertical fuse and method of fabrication
- Patent number 6,218,279
- Issue date Apr 17, 2001
- Infineon Technologies North America Corp.
- Stefan J. Weber
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuits with copper metallization for interconnections
- Patent number 6,146,517
- Issue date Nov 14, 2000
- Infineon Technologies North America Corp.
- Mark D. Hoinkis
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Grant
CVD/PVD method of filling structures using discontinuous CVD AL liner
- Patent number 6,057,236
- Issue date May 2, 2000
- International Business Machines Corporation
- Larry Clevenger
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Process for overcoming CVD aluminum selectivity loss with warm PVD...
- Patent number 5,989,633
- Issue date Nov 23, 1999
- Applied Materials, Inc.
- Mark Hoinkis
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Grant
Method and apparatus for determining wafer warpage for optimized el...
- Patent number 5,872,694
- Issue date Feb 16, 1999
- Siemens Aktiengesellschaft
- Mark Hoinkis
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER

Patents Applicationslast 30 patents

Information Patent Application
METHODS FOR ETCHING A METAL LAYER TO FORM AN INTERCONNECTION STRUCT...
- Publication number 20150287634
- Publication date Oct 8, 2015
- Applied Materials, Inc.
- Sumit AGARWAL
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SELECTIVE SPUTTERING FOR PATTERN TRANSFER
- Publication number 20150014152
- Publication date Jan 15, 2015
- International Business Machines Corporation
- Mark Hoinkis
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Application
COPPER RESIDUE CHAMBER CLEAN
- Publication number 20140345645
- Publication date Nov 27, 2014
- International Business Machines Corporation
- Mark Hoinkis
- B08 - CLEANING
Information Patent Application
SUBTRACTIVE PLASMA ETCHING OF A BLANKET LAYER OF METAL OR METAL ALLOY
- Publication number 20140273437
- Publication date Sep 18, 2014
- Applied Materials, Inc.
- Nicholas C. M. Fuller
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SPUTTER ETCH PROCESSING FOR HEAVY METAL PATTERNING IN INTEGRATED CI...
- Publication number 20140264861
- Publication date Sep 18, 2014
- APPLIED MATERIALS, INCORPORATED
- MARK D. HOINKIS
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method and Apparatus of Stress Relief in Semiconductor Structures
- Publication number 20080213993
- Publication date Sep 4, 2008
- Mark Hoinkis
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Post-etch removal of fluorocarbon-based residues from a hybrid diel...
- Publication number 20070059922
- Publication date Mar 15, 2007
- International Business Machines Corporation
- Lawrence A. Clevenger
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
BACK END INTERCONNECT WITH A SHAPED INTERFACE
- Publication number 20060292852
- Publication date Dec 28, 2006
- International Business Machines Corporation
- Lawrence A. Clevenger
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Bilayered metal hardmasks for use in dual damascene etch schemes
- Publication number 20060113278
- Publication date Jun 1, 2006
- Kaushik Kumar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method and apparatus of stress relief in semiconductor structures
- Publication number 20050221610
- Publication date Oct 6, 2005
- Mark Hoinkis
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
OXIDIZED TANTALUM NITRIDE AS AN IMPROVED HARDMASK IN DUAL-DAMASCENE...
- Publication number 20050208742
- Publication date Sep 22, 2005
- International Business Machines Corporation
- William G. America
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Device interconnection
- Publication number 20050116342
- Publication date Jun 2, 2005
- Lawrence A. Clevenger
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Crystallographic Modification of Hard mask Properties
- Publication number 20050112862
- Publication date May 26, 2005
- International Business Machines Corporation
- Lawrence A. Clevenger
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Application
Back End Interconnect With a Shaped Interface
- Publication number 20050112864
- Publication date May 26, 2005
- International Business Machines Corporation
- Lawrence A. Clevenger
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Stress-relief layer for semiconductor applications
- Publication number 20050093159
- Publication date May 5, 2005
- Hans-Joachim Barth
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Dual damascene structure and method
- Publication number 20050077628
- Publication date Apr 14, 2005
- Kaushik Kumar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Bilayered metal hardmasks for use in dual damascene etch schemes
- Publication number 20040251234
- Publication date Dec 16, 2004
- Kaushik Kumar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method and apparatus of stress relief in semiconductor structures
- Publication number 20040227214
- Publication date Nov 18, 2004
- Mark Hoinkis
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Reduction of the shear stress in copper via's in organic interlayer...
- Publication number 20040175921
- Publication date Sep 9, 2004
- Infineon Technologies North America Corp.
- Andy Cowley
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for depositing a metal layer on a semiconductor interconnect...
- Publication number 20040115921
- Publication date Jun 17, 2004
- International Business Machines Corporation
- Larry Clevenger
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Via liner integration to avoid resistance shift and resist mechanic...
- Publication number 20040058526
- Publication date Mar 25, 2004
- Infineon Technologies North America Corp.
- Andrew Cowley
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Elimination of via-resistance-shift by increasing via size at a las...
- Publication number 20030042580
- Publication date Mar 6, 2003
- Mark Hoinkis
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Chromium adhesion layer for copper vias in low-k technology
- Publication number 20020088117
- Publication date Jul 11, 2002
- Brett H. Engel
- H01 - BASIC ELECTRIC ELEMENTS

Mark Hoinkis

Person

Patents Grantslast 30 patents

Methods for etching a metal layer to form an interconnection struct...

Selective sputtering for pattern transfer

Sputter etch processing for heavy metal patterning in integrated ci...

Sidewall image transfer for heavy metal patterning in integrated ci...

Copper residue chamber clean

Subtractive plasma etching of a blanket layer of metal or metal alloy

Method and apparatus of stress relief in semiconductor structures

Back end interconnect with a shaped interface

Method and apparatus of stress relief in semiconductor structures

Bilayered metal hardmasks for use in dual damascene etch schemes

Method for depositing a metal layer on a semiconductor interconnect...

Back end interconnect with a shaped interface

Dual damascene structure and method

Reduction of the shear stress in copper via's in organic interlayer...

Bilayered metal hardmasks for use in Dual Damascene etch schemes

Crystallographic modification of hard mask properties

Stress-relief layer for semiconductor applications

Device interconnection

Via density rules

Chromium adhesion layer for copper vias in low-k technology

Copper vias in low-k technology

Vertical fuse and method of fabrication

Method of making a microelectronic structure

Tungsten-filled deep trenches

Vertical fuse and method of fabrication

Integrated circuits with copper metallization for interconnections

CVD/PVD method of filling structures using discontinuous CVD AL liner

Process for overcoming CVD aluminum selectivity loss with warm PVD...

Method and apparatus for determining wafer warpage for optimized el...

Patents Applicationslast 30 patents

METHODS FOR ETCHING A METAL LAYER TO FORM AN INTERCONNECTION STRUCT...

SELECTIVE SPUTTERING FOR PATTERN TRANSFER

COPPER RESIDUE CHAMBER CLEAN

SUBTRACTIVE PLASMA ETCHING OF A BLANKET LAYER OF METAL OR METAL ALLOY

SPUTTER ETCH PROCESSING FOR HEAVY METAL PATTERNING IN INTEGRATED CI...

Method and Apparatus of Stress Relief in Semiconductor Structures

Post-etch removal of fluorocarbon-based residues from a hybrid diel...

BACK END INTERCONNECT WITH A SHAPED INTERFACE

Bilayered metal hardmasks for use in dual damascene etch schemes

Method and apparatus of stress relief in semiconductor structures

OXIDIZED TANTALUM NITRIDE AS AN IMPROVED HARDMASK IN DUAL-DAMASCENE...

Device interconnection

Crystallographic Modification of Hard mask Properties

Back End Interconnect With a Shaped Interface

Stress-relief layer for semiconductor applications

Dual damascene structure and method

Bilayered metal hardmasks for use in dual damascene etch schemes

Method and apparatus of stress relief in semiconductor structures

Reduction of the shear stress in copper via's in organic interlayer...

Method for depositing a metal layer on a semiconductor interconnect...

Via liner integration to avoid resistance shift and resist mechanic...

Elimination of via-resistance-shift by increasing via size at a las...

Chromium adhesion layer for copper vias in low-k technology