Mark Tetreault

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Webster, MA, US

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Patents Grantslast 30 patents

Information Patent Grant
Methods and apparatus for computer bus error termination
- Patent number 6,996,750
- Issue date Feb 7, 2006
- Stratus Technologies Bermuda Ltd.
- Mark Tetreault
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Fault-tolerant computer system with voter delay buffer
- Patent number 6,820,213
- Issue date Nov 16, 2004
- Stratus Technologies Bermuda, Ltd.
- Jeffrey S. Somers
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus for generating high-frequency clocks determin...
- Patent number 6,813,721
- Issue date Nov 2, 2004
- Stratus Computer Systems, S.a.r.l.
- Mark Tetreault
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for operating a system with redundant peripheral...
- Patent number 6,708,283
- Issue date Mar 16, 2004
- Stratus Technologies, Bermuda Ltd.
- Robert E. Nelvin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for upgrading fault-tolerant systems
- Patent number 6,687,851
- Issue date Feb 3, 2004
- Stratus Technologies Bermuda Ltd.
- Jeffrey S. Somers
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
Methods and apparatus for computer bus error termination
- Publication number 20020194548
- Publication date Dec 19, 2002
- Mark Tetreault
- G06 - COMPUTING CALCULATING COUNTING