Martin Mazur

Person

Dresden, DE

People

Patents Grantslast 30 patents

Information Patent Grant
Semiconductor device comprising a floating gate flash memory device
- Patent number 9,972,634
- Issue date May 15, 2018
- GLOBALFOUNDRIES Inc.
- Ralf Richter
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Reticles for use in forming implant masking layers and methods of f...
- Patent number 9,372,392
- Issue date Jun 21, 2016
- GLOBALFOUNDRIES Inc.
- Martin Mazur
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
Enhanced patterning uniformity of gate electrodes of a semiconducto...
- Patent number 9,281,200
- Issue date Mar 8, 2016
- GLOBALFOUNDRIES Inc.
- Hans-Juergen Thees
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming self-aligned contacts for a semiconductor device
- Patent number 8,927,407
- Issue date Jan 6, 2015
- GLOBALFOUNDRIES Inc.
- Peter Baars
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Reticles for use in forming implant masking layers and methods of f...
- Patent number 8,802,360
- Issue date Aug 12, 2014
- GLOBALFOUNDRIES Inc.
- Martin Mazur
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
High-k metal gate electrode structures formed by reducing a gate fi...
- Patent number 8,716,120
- Issue date May 6, 2014
- GLOBALFOUNDRIES Inc.
- Klaus Hempel
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Cap layer removal in a high-K metal gate stack by using an etch pro...
- Patent number 8,258,062
- Issue date Sep 4, 2012
- GLOBALFOUNDRIES Inc.
- Ralf Richter
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Enhanced stress transfer in an interlayer dielectric by using an ad...
- Patent number 7,994,059
- Issue date Aug 9, 2011
- Advanced Micro Devices, Inc.
- Ralf Richter
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Enhanced cap layer integrity in a high-K metal gate stack by using...
- Patent number 7,981,740
- Issue date Jul 19, 2011
- GLOBALFOUNDRIES Inc.
- Markus Lenski
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Arc layer having a reduced flaking tendency and a method of manufac...
- Patent number 7,938,973
- Issue date May 10, 2011
- Advanced Micro Devices, Inc.
- Ralf Richter
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of detecting repeating defects in lithography masks on the b...
- Patent number 7,887,978
- Issue date Feb 15, 2011
- GLOBALFOUNDRIES Inc.
- Uwe Griebenow
- G01 - MEASURING TESTING
Information Patent Grant
Method for reducing resist poisoning during patterning of silicon n...
- Patent number 7,550,396
- Issue date Jun 23, 2009
- Advanced Micro Devices, Inc.
- Kai Frohberg
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Advanced process control model incorporating a target offset term
- Patent number 7,547,561
- Issue date Jun 16, 2009
- Advanced Micro Devices, Inc.
- Uwe Schulze
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Technique for controlling mechanical stress in a channel region by...
- Patent number 7,314,793
- Issue date Jan 1, 2008
- Advanced Micro Devices, Inc.
- Kai Frohberg
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of defining the dimensions of circuit elements by using spac...
- Patent number 6,936,383
- Issue date Aug 30, 2005
- Advanced Micro Devices, Inc.
- Martin Mazur
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods and systems for controlling resist residue defects at gate...
- Patent number 6,759,179
- Issue date Jul 6, 2004
- Advanced Micro Devices, Inc.
- Khoi A. Phan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods and systems for controlling resist residue defects at gate...
- Patent number 6,649,525
- Issue date Nov 18, 2003
- Advanced Micro Devices, Inc.
- Khoi A. Phan
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
SEMICONDUCTOR DEVICE COMPRISING A FLOATING GATE FLASH MEMORY DEVICE
- Publication number 20180047738
- Publication date Feb 15, 2018
- GLOBALFOUNDRIES INC.
- Ralf Richter
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
RETICLES FOR USE IN FORMING IMPLANT MASKING LAYERS AND METHODS OF F...
- Publication number 20140329173
- Publication date Nov 6, 2014
- Martin Mazur
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Application
RETICLES FOR USE IN FORMING IMPLANT MASKING LAYERS AND METHODS OF F...
- Publication number 20140030637
- Publication date Jan 30, 2014
- GLOBALFOUNDRIES INC.
- Martin Mazur
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Application
Method of Forming Self-Aligned Contacts for a Semiconductor Device
- Publication number 20130189833
- Publication date Jul 25, 2013
- GLOBALFOUNDRIES INC.
- Peter Baars
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HIGH-K METAL GATE ELECTRODE STRUCTURES FORMED BY REDUCING A GATE FI...
- Publication number 20120319205
- Publication date Dec 20, 2012
- GLOBALFOUNDRIES INC.
- Klaus Hempel
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Enhanced Patterning Uniformity of Gate Electrodes of a Semiconducto...
- Publication number 20120156865
- Publication date Jun 21, 2012
- GLOBALFOUNDRIES INC.
- Hans-Juergen Thees
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ENHANCED CAP LAYER INTEGRITY IN A HIGH-K METAL GATE STACK BY USING...
- Publication number 20100330757
- Publication date Dec 30, 2010
- Markus Lenski
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CAP LAYER REMOVAL IN A HIGH-K METAL GATE STACK BY USING AN ETCH PRO...
- Publication number 20100330808
- Publication date Dec 30, 2010
- Ralf Richter
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD OF DETECTING REPEATING DEFECTS IN LITHOGRAPHY MASKS ON THE B...
- Publication number 20090274981
- Publication date Nov 5, 2009
- Uwe Griebenow
- G01 - MEASURING TESTING
Information Patent Application
ENHANCED STRESS TRANSFER IN AN INTERLAYER DIELECTRIC BY USING AN AD...
- Publication number 20080179661
- Publication date Jul 31, 2008
- Ralf Richter
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ARC LAYER HAVING A REDUCED FLAKING TENDENCY AND A METHOD OF MANUFAC...
- Publication number 20080078738
- Publication date Apr 3, 2008
- Ralf Richter
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR REDUCING RESIST POISONING DURING PATTERNING OF SILICON N...
- Publication number 20080081480
- Publication date Apr 3, 2008
- Kai Frohberg
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Advanced process control model incorporating a target offset term
- Publication number 20060223203
- Publication date Oct 5, 2006
- Uwe Schulze
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method of patterning a layer of a material
- Publication number 20060172518
- Publication date Aug 3, 2006
- Kai Frohberg
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Application
Techique for controlling mechanical stress in a channel region by s...
- Publication number 20050266639
- Publication date Dec 1, 2005
- Kai Frohberg
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method of forming sidewall spacers
- Publication number 20050233532
- Publication date Oct 20, 2005
- Markus Lenski
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method of defining the dimensions of circuit elements by using spac...
- Publication number 20040002217
- Publication date Jan 1, 2004
- Martin Mazur
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor structure having a silicon oxynitride ARC layer and a...
- Publication number 20020076843
- Publication date Jun 20, 2002
- Hartmut Ruelke
- H01 - BASIC ELECTRIC ELEMENTS

Martin Mazur

Person

Patents Grantslast 30 patents

Semiconductor device comprising a floating gate flash memory device

Reticles for use in forming implant masking layers and methods of f...

Enhanced patterning uniformity of gate electrodes of a semiconducto...

Method of forming self-aligned contacts for a semiconductor device

Reticles for use in forming implant masking layers and methods of f...

High-k metal gate electrode structures formed by reducing a gate fi...

Cap layer removal in a high-K metal gate stack by using an etch pro...

Enhanced stress transfer in an interlayer dielectric by using an ad...

Enhanced cap layer integrity in a high-K metal gate stack by using...

Arc layer having a reduced flaking tendency and a method of manufac...

Method of detecting repeating defects in lithography masks on the b...

Method for reducing resist poisoning during patterning of silicon n...

Advanced process control model incorporating a target offset term

Technique for controlling mechanical stress in a channel region by...

Method of defining the dimensions of circuit elements by using spac...

Methods and systems for controlling resist residue defects at gate...

Methods and systems for controlling resist residue defects at gate...

Patents Applicationslast 30 patents

SEMICONDUCTOR DEVICE COMPRISING A FLOATING GATE FLASH MEMORY DEVICE

RETICLES FOR USE IN FORMING IMPLANT MASKING LAYERS AND METHODS OF F...

RETICLES FOR USE IN FORMING IMPLANT MASKING LAYERS AND METHODS OF F...

Method of Forming Self-Aligned Contacts for a Semiconductor Device

HIGH-K METAL GATE ELECTRODE STRUCTURES FORMED BY REDUCING A GATE FI...

Enhanced Patterning Uniformity of Gate Electrodes of a Semiconducto...

ENHANCED CAP LAYER INTEGRITY IN A HIGH-K METAL GATE STACK BY USING...

CAP LAYER REMOVAL IN A HIGH-K METAL GATE STACK BY USING AN ETCH PRO...

METHOD OF DETECTING REPEATING DEFECTS IN LITHOGRAPHY MASKS ON THE B...

ENHANCED STRESS TRANSFER IN AN INTERLAYER DIELECTRIC BY USING AN AD...

ARC LAYER HAVING A REDUCED FLAKING TENDENCY AND A METHOD OF MANUFAC...

METHOD FOR REDUCING RESIST POISONING DURING PATTERNING OF SILICON N...

Advanced process control model incorporating a target offset term

Method of patterning a layer of a material

Techique for controlling mechanical stress in a channel region by s...

Method of forming sidewall spacers

Method of defining the dimensions of circuit elements by using spac...

Semiconductor structure having a silicon oxynitride ARC layer and a...