Martin Schnell

Person

Worblingen, DE

People

Patents Grantslast 30 patents

Information Patent Grant
Method for visualizing spatially-resolved measurement results and c...
- Patent number 9,667,890
- Issue date May 30, 2017
- Testo AG
- Martin Schnell
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Test method, integrated circuit and test system
- Patent number 7,757,145
- Issue date Jul 13, 2010
- Qimonda AG
- Wolfgang Ruf
- G11 - INFORMATION STORAGE
Information Patent Grant
Circuit arrangement and method for driving electronic chips
- Patent number 7,426,669
- Issue date Sep 16, 2008
- Infineon Technologies AG
- Björn Flach
- G11 - INFORMATION STORAGE
Information Patent Grant
Insertable calibration device
- Patent number 7,414,421
- Issue date Aug 19, 2008
- Infineon Technologies AG
- Björn Flach
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor component, arrangement and method for characterizing...
- Patent number 7,360,139
- Issue date Apr 15, 2008
- Infineon Technologies AG
- Andreas Logisch
- G11 - INFORMATION STORAGE
Information Patent Grant
Backwards-compatible memory module
- Patent number 7,221,617
- Issue date May 22, 2007
- Infineon Technologies AG
- Bjorn Flach
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory chip, memory component and corresponding memory module and m...
- Patent number 6,947,303
- Issue date Sep 20, 2005
- Infineon Technologies AG
- Martin Schnell
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and magazine device for testing semiconductor devices
- Patent number 6,777,924
- Issue date Aug 17, 2004
- Infineon Technologies AG
- Björn Flach
- G01 - MEASURING TESTING

Patents Applicationslast 30 patents

Information Patent Application
METHOD FOR VISUALIZING SPATIALLY-RESOLVED MEASUREMENT RESULTS AND C...
- Publication number 20120257049
- Publication date Oct 11, 2012
- Testo AG
- Martin Schnell
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Test method, integrated circuit and test system
- Publication number 20080288835
- Publication date Nov 20, 2008
- Qimonda AG
- Wolfgang Ruf
- G11 - INFORMATION STORAGE
Information Patent Application
Integrated circuit arrangement
- Publication number 20070176255
- Publication date Aug 2, 2007
- Franz Kreupl
- G11 - INFORMATION STORAGE
Information Patent Application
Method for testing a circuit unit and test apparatus
- Publication number 20060181300
- Publication date Aug 17, 2006
- Bjorn Flach
- G01 - MEASURING TESTING
Information Patent Application
Semiconductor component, arrangement and method for characterizing...
- Publication number 20060156149
- Publication date Jul 13, 2006
- Andreas Logisch
- G11 - INFORMATION STORAGE
Information Patent Application
Insertable calibration device
- Publication number 20060149491
- Publication date Jul 6, 2006
- Infineon Technologies AG
- Bjorn Flach
- G01 - MEASURING TESTING
Information Patent Application
Backwards-compatible memory module
- Publication number 20050270891
- Publication date Dec 8, 2005
- Bjorn Flach
- G11 - INFORMATION STORAGE
Information Patent Application
Circuit arrangement and method for driving electronic chips
- Publication number 20050138491
- Publication date Jun 23, 2005
- Infineon Technologies AG
- Bjorn Flach
- G01 - MEASURING TESTING
Information Patent Application
Test arrangement and method for selecting a test mode output channel
- Publication number 20050055618
- Publication date Mar 10, 2005
- Thomas Finteis
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Memory chip, memory component and corresponding memory module and m...
- Publication number 20030185082
- Publication date Oct 2, 2003
- Martin Schnell
- G11 - INFORMATION STORAGE
Information Patent Application
Method and magazine device for testing semiconductor devices
- Publication number 20030173950
- Publication date Sep 18, 2003
- Bjorn Flach
- G01 - MEASURING TESTING

Martin Schnell

Person

Patents Grantslast 30 patents

Method for visualizing spatially-resolved measurement results and c...

Test method, integrated circuit and test system

Circuit arrangement and method for driving electronic chips

Insertable calibration device

Semiconductor component, arrangement and method for characterizing...

Backwards-compatible memory module

Memory chip, memory component and corresponding memory module and m...

Method and magazine device for testing semiconductor devices

Patents Applicationslast 30 patents

METHOD FOR VISUALIZING SPATIALLY-RESOLVED MEASUREMENT RESULTS AND C...

Test method, integrated circuit and test system

Integrated circuit arrangement

Method for testing a circuit unit and test apparatus

Semiconductor component, arrangement and method for characterizing...

Insertable calibration device

Backwards-compatible memory module

Circuit arrangement and method for driving electronic chips

Test arrangement and method for selecting a test mode output channel

Memory chip, memory component and corresponding memory module and m...

Method and magazine device for testing semiconductor devices