Patent Application
20070176255
The invention relates to an integrated circuit arrangement.
In many integrated circuits, for example, in many semiconductor integrated circuits, a permanent memory is required for storing binary data, which can be written once and which can be read an arbitrary number of times. An example of such an integrated circuit is a so-called programmable read only memory (PROM).
Furthermore, permanent storage cells are also required in a dynamic random access memory (DRAM) in order to store information about defect cells to be masked out, or in order to permanently match operation parameter.
One possibility of storing the information is using so-called laser fuses. Laser fuses are to be understood electrically conductive connections at the surface of the integrated circuit, which can be interrupted by means of a focused laser beam.
However, disadvantages of laser fuses may be seen in:
a) the remarkable size of the laser fuse circuits, the scaling down of which is limited by the wavelength of the laser that is used for melting the laser fuses; and
b) the fact that after molding the integrated circuit arrangement in a package, it is no longer possible to change the fuses; for this reason, it is not possible to mask out defects of cells, which occur after the molding, thereby reducing the yield.
In order to overcome the above disadvantages of the laser fuses, so-called electronic fuses are examined, wherein the electrically conductive connection can be disconnected by means of a short high current pulse. However, the electronic fuses suffer from little reliability, since no material removal of the electrically conductive connection material to the outside of the integrated circuit is possible in a closed, i.e., packaged integrated circuit. For this reason, the material of the disconnected electrically conductive connection can step by step form an electrically conductive structure again. Thus, the information written by disconnecting the electrically conductive connection may be lost again.
The integrated circuit arrangement according to a first aspect of the invention, comprises at least one one-time programmable storage element having at least one electrically conductive or semi-conductive nanotube or at least one electrically conductive or semi-conductive nanowire.
According to a second aspect of the invention, the integrated circuit arrangement comprises a first electronic terminal, a second electronic terminal and at least one one-time programmable storage element having at least one electrically conductive or semi-conductive nanotube or at least one electrically conductive or semi-conductive nanowire being coupled to the first electronic terminal and to the second electronic terminal.
According to a third aspect of the invention, the integrated circuit arrangement comprises a plurality of electronic terminals and a plurality of one-time programmable storage elements, each having at least one electrically conductive or semi-conductive nanotube or at least one electrically conductive or semi-conductive nanowire and being coupled to at least two of the electronic terminals.
A method for manufacturing an integrated circuit arrangement in accordance with a fourth aspect of the invention includes, providing a first electronic terminal, providing a second electronic terminal, providing at least one one-time programmable storage element having at least one electrically conductive or semi-conductive nanotube, or at least one electrically conductive or semi-conductive nanowire by coupling it to the first electronic terminal and to the second electronic terminal.
The method for programming an integrated circuit arrangement having a plurality of electronic terminals and a plurality of one-time programmable storage elements, each having at least one electrically conductive or semi-conductive nanotube or at least one electrically conductive or semi-conductive nanowire and being coupled to at least two of the electronic terminals, in accordance with a fifth aspect of the invention, comprises selectively deactivating one or a plurality of nanotubes or one or a plurality of nanowires.
The invention clearly achieves an electronic fuse element in an integrated circuit providing increased reliability.
These and other features of the invention will be better understood when taken in view of the following drawings and a detailed description.
For a more complete understanding of the present invention, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:
The following list of reference symbols can be used in conjunction with the figures:
The making and using of the presently preferred embodiments are discussed in detail below. It should be appreciated, however, that the present invention provides many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways to make and use the invention, and do not limit the scope of the invention.
In accordance with one aspect of the invention, the one-time programmable storage element is an electronic fuse element.
In accordance with another aspect of the invention, the at least one electrically conductive or semi-conductive nanotube is made of carbon. One or a plurality of carbon nanotubes may be provided in order to be programmed by means of electrically fusing them.
According to another embodiment of the invention, the at least one electrically conductive or semi-conductive nanowire is made of a material selected from:
One or a plurality of nanowires, e.g., made of one or a plurality of the above materials, may be provided in order to be programmed by electrically fusing them.
Furthermore, a fuse element programming unit for providing an electrical current to the at least one fuse element for programming the at least one fuse element may be provided. The fuse element programming unit may comprise one or a plurality of conducting tracks and, optionally, in addition, one or a plurality of energy sources, e.g., one or a plurality of current sources.
One embodiment of the method for manufacturing an integrated circuit arrangement, comprises providing the first electronic terminal comprises arranging the first electronic terminal on a substrate. Alternatively or in addition to this embodiment of the invention, the second electronic terminal may be arranged on a substrate.
The nanotube(s) may be deposited or grown on the substrate, e.g., by depositing the nanotube(s) out of the liquid phase.
Before depositing the nanotube(s) or the nanowire(s) on the substrate, the surface of the substrate may be sensitized, thereby further improving the bonding of them to the surface of the substrate. Silane groups may be used for sensitizing the surface of the substrate.
According to another aspect of the invention, non-desired nanotubes or nanowires may be removed by means of etching.
One embodiment of the method for programming an integrated circuit arrangement, comprises selectively deactivating one or a plurality of nanotubes or one or a plurality of nanowires comprising selectively destroying one or a plurality of nanotubes or one or a plurality of nanowires.
The invention is particularly suitable for the application in a memory circuit, e.g., a volatile memory circuit (e.g., a dynamic random access memory (DRAM), alternatively a non-volatile memory circuit. In accordance with this embodiment of the invention, the non-volatile memory circuit may be one selected from the group of:
It is to be noted that, although the embodiment of the invention will now be described with respect to DRAM volatile memory cell array comprising a plurality of DRAM cells, the invention is applicable to any suitable integrated circuit, e.g., clearly as a one-time programmable read only memory.
The electronic fuse element 200, which is provided on a surface of a substrate (not shown in
At least one carbon nanotube 206 (e.g., a single wall carbon nanotube or a multi-wall carbon nanotube, wherein the carbon nanotube may be doped or undoped) is arranged between the first metallic terminal 202 and the second metallic terminal 204. A first end portion 208 of the carbon nanotube 206 is mechanically and electrically coupled to the first metallic terminal 202. A second end portion 210 of the carbon nanotube 206 is mechanically and electrically coupled to the second metallic terminal 204.
A programming current 212 for melting the carbon nanotube 206 is provided by a current source and is guided through the second metallic terminal 204 and through the carbon nanotube 206 to the first metallic terminal 202, thereby heating and melting the carbon nanotube 206, if desired. Furthermore, if it is to be determined as to whether the carbon nanotube 206 is deactivated, e.g., destroyed, a read current is provided by the current source and is guided through the second metallic terminal 204 and, if activated, through the carbon nanotube 206 to the first metallic terminal 202, where the resulting current is sensed and the resistance of the connection is determined, thereby determining as to whether the carbon nanotube 206 is deactivated (non-conducting) or active (metallically conducting or semi-conducting).
The electronic fuse element 300, which is provided on a surface of a substrate, according to this exemplary embodiment of the invention a non-conducting layer 402 (see cross-sectional view 400 of region A of the electronic fuse element 300 of
According to this exemplary embodiment of the invention, a plurality of carbon nanotubes 306 (e.g., single wall carbon nanotubes or multi-wall carbon nanotubes, wherein the carbon nanotubes may be doped or undoped), in an alternative embodiment of the invention a plurality of silicon nanowires, is arranged between the first metal contact 302 and the second metal contact 304. A respective first end portion of the carbon nanotubes 306 or nanowires is mechanically and electrically coupled to the first metal contact 302. A respective second end portion of the carbon nanotubes 306 or nanowires is mechanically and electrically coupled to the second metal contact 304.
The integrated circuit arrangement 500 comprises a plurality of electronic terminals 504, which are arranged on a substrate 502 in a matrix of rows and columns although they may be arranged in a different arrangement in alternative embodiments, e.g., in a hexagonal arrangement. The electronic terminals 504 are spaced apart from each other and, since the surface of the substrate is electrically isolating, they are also electrically isolated from each other.
It should be mentioned that the nanotube fuses or one-time-programming (OTP) storage elements can be provided with the carbon nanotubes in a front end of line (FEOL) process or in a back end of line (BEOL) process.
In principal, carbon nanotubes 506 are deposited on or at pre-manufactured structures (see
The density of the tubes may be influenced and controlled by controlling the growth or the way of the application of the suspension.
According to one exemplary embodiment of the invention, the surface of the substrate can be sensitized using silane groups in order to achieve a controlled (at predetermined positions preferred) deposition of the carbon nanotubes 506. However, this is not necessary in accordance with the exemplary embodiments of the invention.
The carbon nanotubes 506 are coupled to the electronic terminals 502 e.g., by means of van der Waals force.
After the carbon nanotubes 506 have been deposited, the desired pattern matrix is defined by means of photo resist structuring.
Existing carbon nanotube bridges (in other words carbon nanotube connections) between electronic terminals 502, which are not desired, are removed by means of a short oxygen dry etch process or by means of a short hydrogen dry etch process in a very easy manner.
The remaining carbon nanotube structure forms the electronic fuse element structure 508 (see
According to an exemplary embodiment of the invention, an electrical current of approximately 20 μA to 30 μA is provided for each carbon nanotube and is flowing through the respective carbon nanotube in order to deactivate them. Alternatively, the occurring electrical fields in the respective carbon nanotube should be greater than approximately 1 Volt/100 nm (approximately 105 V/cm).
In alternative embodiments of the invention any method that is suitable for deactivating the carbon nanotubes, generally speaking, the nanotubes or nanowires, can be used, e.g., the methods for providing electrical breakdown of single wall carbon nanotubes, which are described in R. V. Seidel et. al., “Bias dependence and electrical breakdown of small diameter single-walled carbon nanotubes,” Journal of Applied Physics, Volume 96, Number 11, pages 6694 to 6699, December 2004, which is herewith fully incorporated by reference.
The DRAM 600 comprises, inter alia, an array 601 of a plurality of volatile memory cells 602, each memory cell having, for example, a select transistor, a capacitor and a resistor. The array 601 further has redundancy volatile memory cells 606, which are only used in case a “regular” volatile memory cell 602 within the array 601 is defect and needs to be replaced by a redundancy volatile memory cell 606 of a redundancy region within the array 601.
The volatile memory cells 602 are arranged in rows and columns within the array 601. Furthermore, an address decoder 603 is provided which determines the address of the respective volatile memory cell 602 within the array 601 upon receipt of a global cell address 614. The address decoder 603 further determines, upon a request to read a respective volatile memory cell 602, whether the requested volatile memory cell 602 in the array 601 is marked as being a defect volatile memory cell 604 or not.
If the determined volatile memory cell 602 is not marked as defect, the content of the respective volatile memory cell 602 is read (indicated in
The information as to whether a respective volatile memory cell 602 is defect or not, generally speaking, the information about defect regions within the array 601, is, according to this exemplary embodiment of the invention, stored in a permanent, one time programmable (OTP) memory, that is formed by means of an array 612 of, e.g., one time programmable (OTP), electronic fuses as they are described above.
However, it should be noted, that the invention can be provided in any kind of memory arrangement, e.g., a non-volatile memory arrangement, for example one of the following types of non-volatile memory arrangements, e.g., to store information about defect memory cells:
Furthermore, the invention can also be used as a programmable read only memory (PROM).
One aspect of the invention may clearly be seen in the provision of a write-once storage element comprising at least one deactivatable nanotube or at least one deactivatable nanowire.
In other words, one aspect of the invention may be seen in a nanotube or nanowire interconnection between two metal electrodes per memory cell. The nanotube or nanowire acts as a fuse-like resistor. The resistance can e.g., be changed once by applying a current pulse destroying the nanotube or nanowire so that the resistance of the interconnection is increased.
As an example, it is assumed that one nanotube (e.g., a carbon nanotube) can carry up to 24 μA and that the resistance of a nanotube varies between 7 KOhm and 10 Mohm, depending on the type of nanotube that is used. In order to provide a rough estimation, it is further assumed that there are 100 nanotubes provided, each nanotube having a resistance of 7 KOhm, connecting two metal electrodes (contacts) of an unblown electronic fuse, wherein the resistance of the entirety of unblown nanotubes, which are connected in parallel, is 70 Ohm. The current required to destroy the nanotubes then should be greater than 100*24 μA=2.4 mA. This would require a voltage of approximately 24 μA*7 Kohm=0.17 V. After the nanotubes have been destroyed, the resistance of the (clearly no longer existing) interconnection between the metal contacts should be very high. The resistance can be measured by applying a small measurement current through the two metal contacts and the interconnection formed by the nanotubes.
According to one aspect of the invention, the coding of the storage elements (deactivated and remained activated nanotubes or nanowires) is not resettable, but the coding can be provided even after the molding of the integrated circuit arrangement.
Thus, if the coding is selected in a suitable manner, it is possible to mask out cells, e.g., storage cells, even if it is recognized that they are defect only after the completion of the manufacturing of the respective component
Various aspects of the invention provide, inter alia, the following advantages:
The foregoing description has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed, and obviously many modifications and variations are possible in light of the disclosed teaching. The described embodiments were chosen in order to best explain the principles of the invention and its practical application to thereby enable others skilled in the art to best utilize the invention in various embodiments and with various modifications as are suited to the particular use contemplated. It is intended that the scope of the invention be defined by the claims appended hereto.
