Masaru Yano

Person

Sunnyvale, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Dual bit memory device with isolated polysilicon floating gates
- Patent number 6,713,809
- Issue date Mar 30, 2004
- Advanced Micro Devices, Inc.
- Jusuke Ogura
- G11 - INFORMATION STORAGE
Information Patent Grant
Multi-set block erase
- Patent number 6,622,230
- Issue date Sep 16, 2003
- Advanced Micro Devices, Inc.
- Masaru Yano
- G11 - INFORMATION STORAGE
Information Patent Grant
Process for making a dual bit memory device with isolated polysilic...
- Patent number 6,573,140
- Issue date Jun 3, 2003
- Advanced Micro Devices, Inc.
- Jusuke Ogura
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Output drivers for integrated-circuit chips with VCCQ supply compen...
- Patent number 6,323,687
- Issue date Nov 27, 2001
- Fujitsu Limited
- Masaru Yano
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Sensing time control device and method
- Patent number 6,304,486
- Issue date Oct 16, 2001
- Fujitsu Limited
- Masaru Yano
- G11 - INFORMATION STORAGE
Information Patent Grant
Scheme for page erase and erase verify in a non-volatile memory array
- Patent number 5,995,417
- Issue date Nov 30, 1999
- Advanced Micro Devices, Inc.
- Pau-Ling Chen
- G11 - INFORMATION STORAGE
Information Patent Grant
Bit line biasing method to eliminate program disturbance in a non-v...
- Patent number 5,978,267
- Issue date Nov 2, 1999
- Advanced Micro Devices, Inc.
- Pau-Ling Chen
- G11 - INFORMATION STORAGE
Information Patent Grant
Shift register functioning in both latch mode and counter mode and...
- Patent number 5,926,520
- Issue date Jul 20, 1999
- Fujitsu Limited
- Masaru Yano
- G11 - INFORMATION STORAGE
Information Patent Grant
High voltage NMOS pass gate for integrated circuit with high voltag...
- Patent number 5,852,576
- Issue date Dec 22, 1998
- Advanced Micro Devices, Inc.
- Binh Quang Le
- G11 - INFORMATION STORAGE
Information Patent Grant
High voltage NMOS pass gate for integrated circuit with high voltag...
- Patent number 5,801,579
- Issue date Sep 1, 1998
- Advanced Micro Devices, Inc.
- Binh Quang Le
- G11 - INFORMATION STORAGE

Masaru Yano

Person

Patents Grantslast 30 patents

Dual bit memory device with isolated polysilicon floating gates

Multi-set block erase

Process for making a dual bit memory device with isolated polysilic...

Output drivers for integrated-circuit chips with VCCQ supply compen...

Sensing time control device and method

Scheme for page erase and erase verify in a non-volatile memory array

Bit line biasing method to eliminate program disturbance in a non-v...

Shift register functioning in both latch mode and counter mode and...

High voltage NMOS pass gate for integrated circuit with high voltag...

High voltage NMOS pass gate for integrated circuit with high voltag...