Massimo SUTERA

Person

Sunnyvale, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Extending functionality of memory controllers in a processor-based...
- Patent number 12,159,056
- Issue date Dec 3, 2024
- Ampere Computing LLC
- Massimo Sutera
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Parity protected memory blocks merged with error correction code (E...
- Patent number 11,934,263
- Issue date Mar 19, 2024
- Ampere Computing LLC
- Massimo Sutera
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System address reconstruction
- Patent number 10,162,750
- Issue date Dec 25, 2018
- Intel Corporation
- Massimo Sutera
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method for a non-power-of-2 size cache in a first lev...
- Patent number 10,042,562
- Issue date Aug 7, 2018
- Intel Corporation
- Vedaraman Geetha
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Implementation of reserved cache slots in computing system having i...
- Patent number 10,007,606
- Issue date Jun 26, 2018
- Intel Corporation
- Vedaraman Geetha
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method for a non-power-of-2 size cache in a first lev...
- Patent number 9,747,041
- Issue date Aug 29, 2017
- Intel Corporation
- Vedaraman Geetha
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Efficient implementation of geometric series
- Patent number 9,734,054
- Issue date Aug 15, 2017
- Intel Corporation
- Massimo Sutera
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for reordering memory accesses to reduce power...
- Patent number 7,721,011
- Issue date May 18, 2010
- Oracle America, Inc.
- Massimo Sutera
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for reducing noise in integrated circuit layouts
- Patent number 6,832,180
- Issue date Dec 14, 2004
- Sun Microsystems, Inc.
- Massimo Sutera
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
PARITY PROTECTED MEMORY BLOCKS MERGED WITH ERROR CORRECTION CODE (E...
- Publication number 20240220356
- Publication date Jul 4, 2024
- Ampere Computing LLC
- Massimo Sutera
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
EXTENDING FUNCTIONALITY OF MEMORY CONTROLLERS IN A PROCESSOR-BASED...
- Publication number 20240004577
- Publication date Jan 4, 2024
- Ampere Computing LLC
- Massimo Sutera
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTEGRATED ERROR CORRECTION CODE (ECC) AND PARITY PROTECTION IN MEM...
- Publication number 20230315571
- Publication date Oct 5, 2023
- Ampere Computing LLC
- Massimo Sutera
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PARITY PROTECTED MEMORY BLOCKS MERGED WITH ERROR CORRECTION CODE (E...
- Publication number 20230315565
- Publication date Oct 5, 2023
- Ampere Computing LLC
- Massimo Sutera
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUS AND METHOD FOR A NON-POWER-OF-2 SIZE CACHE IN A FIRST LEV...
- Publication number 20180004433
- Publication date Jan 4, 2018
- Intel Corporation
- Vedaraman Geetha
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Implementation of Reserved Cache Slots in Computing System Having I...
- Publication number 20170286298
- Publication date Oct 5, 2017
- Intel Corporation
- Vedaraman GEETHA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUS AND METHOD FOR A NON-POWER-OF-2 SIZE CACHE IN A FIRST LEV...
- Publication number 20170185315
- Publication date Jun 29, 2017
- Intel Corporation
- Vedaraman Geetha
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM ADDRESS RECONSTRUCTION
- Publication number 20170177477
- Publication date Jun 22, 2017
- Intel Corporation
- Massimo SUTERA
- G06 - COMPUTING CALCULATING COUNTING

Massimo SUTERA

Person

Patents Grantslast 30 patents

Extending functionality of memory controllers in a processor-based...

Parity protected memory blocks merged with error correction code (E...

System address reconstruction

Apparatus and method for a non-power-of-2 size cache in a first lev...

Implementation of reserved cache slots in computing system having i...

Apparatus and method for a non-power-of-2 size cache in a first lev...

Efficient implementation of geometric series

Method and apparatus for reordering memory accesses to reduce power...

Method for reducing noise in integrated circuit layouts

Patents Applicationslast 30 patents

PARITY PROTECTED MEMORY BLOCKS MERGED WITH ERROR CORRECTION CODE (E...

EXTENDING FUNCTIONALITY OF MEMORY CONTROLLERS IN A PROCESSOR-BASED...

INTEGRATED ERROR CORRECTION CODE (ECC) AND PARITY PROTECTION IN MEM...

PARITY PROTECTED MEMORY BLOCKS MERGED WITH ERROR CORRECTION CODE (E...

APPARATUS AND METHOD FOR A NON-POWER-OF-2 SIZE CACHE IN A FIRST LEV...

Implementation of Reserved Cache Slots in Computing System Having I...

APPARATUS AND METHOD FOR A NON-POWER-OF-2 SIZE CACHE IN A FIRST LEV...

SYSTEM ADDRESS RECONSTRUCTION