Matthew BERZINS

Person

Cedar Park, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
Method for reducing power consumption in scannable flip-flops witho...
- Patent number 11,092,649
- Issue date Aug 17, 2021
- Samsung Electronics Co., Ltd.
- Matthew Berzins
- G01 - MEASURING TESTING
Information Patent Grant
Low-power low-setup integrated clock gating cell with complex enabl...
- Patent number 10,819,342
- Issue date Oct 27, 2020
- Samsung Electronics Co., Ltd.
- Matthew Berzins
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Low power integrated clock gating system and method
- Patent number 10,784,864
- Issue date Sep 22, 2020
- Samsung Electronics Co., Ltd.
- Matthew Berzins
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Power rail for standard cell block
- Patent number 10,784,198
- Issue date Sep 22, 2020
- Samsung Electronics Co., Ltd.
- Rwik Sengupta
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Power grid and standard cell co-design structure and methods thereof
- Patent number 10,748,889
- Issue date Aug 18, 2020
- Samsung Electronics Co., Ltd.
- Matthew Berzins
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for improving scan hold-time violation and low vo...
- Patent number 10,720,204
- Issue date Jul 21, 2020
- Samsung Electronics Co., Ltd.
- Matthew Berzins
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Layout connection isolation technique for improving immunity to jit...
- Patent number 10,607,982
- Issue date Mar 31, 2020
- Samsung Electronics Co., Ltd.
- Matthew Berzins
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
High speed domino-based flip flop
- Patent number 10,581,410
- Issue date Mar 3, 2020
- Samsung Electronics Co., Ltd.
- Matthew Berzins
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Dynamic flip flop having data independent P-stack feedback
- Patent number 10,382,017
- Issue date Aug 13, 2019
- Samsung Electronics Co., Ltd.
- Matthew Berzins
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Multi-bit flip-flops
- Patent number 10,353,000
- Issue date Jul 16, 2019
- Samsung Electronics Co., Ltd.
- Doo-Seok Yoon
- G01 - MEASURING TESTING
Information Patent Grant
Low power integrated clock gating cell using controlled inverted clock
- Patent number 10,298,235
- Issue date May 21, 2019
- Samsung Electronics Co., Ltd.
- James Jung Lim
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
System and method for improving scan hold-time violation and low vo...
- Patent number 10,262,723
- Issue date Apr 16, 2019
- Samsung Electronics Co., Ltd.
- Matthew Berzins
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Using deep sub-micron stress effects and proximity effects to creat...
- Patent number 9,904,758
- Issue date Feb 27, 2018
- Samsung Electronics Co., Ltd.
- Matthew Berzins
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Semiconductor circuit including flip-flop
- Patent number 9,899,990
- Issue date Feb 20, 2018
- Samsung Electronics Co., Ltd.
- San-Ha Kim
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Flip-flop with zero-delay bypass mux
- Patent number 9,793,881
- Issue date Oct 17, 2017
- Samsung Electronics Co., Ltd.
- Christina Wells
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Low power minimal disruptive method to implement large quantity pus...
- Patent number 9,779,201
- Issue date Oct 3, 2017
- Samsung Electronics Co., Ltd.
- Brian Millar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Low power integrated clock gating cell with internal control signal
- Patent number 9,768,756
- Issue date Sep 19, 2017
- Samsung Electronics Co., Ltd.
- James Jung Lim
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Apparatus for low power high speed integrated clock gating cell
- Patent number 9,564,897
- Issue date Feb 7, 2017
- Samsung Electronics Co., Ltd.
- Matthew Berzins
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Integrated clock gater (ICG) using clock cascode complimentary swit...
- Patent number 9,450,578
- Issue date Sep 20, 2016
- Samsung Electronics Co., Ltd.
- Matthew S. Berzins
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Low power toggle latch-based flip-flop including integrated clock g...
- Patent number 9,419,590
- Issue date Aug 16, 2016
- Samsung Electronics Co., Ltd.
- Matthew Berzins
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Integrated clock gater (ICG) using clock cascode complimentary swit...
- Patent number 9,203,382
- Issue date Dec 1, 2015
- Samsung Electronics Co., Ltd.
- Matthew S. Berzins
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Integrated clock gater (ICG) using clock cascode complimentary swit...
- Patent number 8,975,949
- Issue date Mar 10, 2015
- Samsung Electronics Co., Ltd.
- Matthew S. Berzins
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Pulsed state retention power gating flip-flop
- Patent number 8,289,060
- Issue date Oct 16, 2012
- FREESCALE SEMICONDUCTOR, INC.
- Samuel J. Tower
- G11 - INFORMATION STORAGE
Information Patent Grant
Linearized digital phase-locked loop method for maintaining end of...
- Patent number 7,826,581
- Issue date Nov 2, 2010
- Cypress Semiconductor Corporation
- Stephen M. Prather
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Circuitry and method for buffering a power mode control signal
- Patent number 7,683,697
- Issue date Mar 23, 2010
- FREESCALE SEMICONDUCTOR, INC.
- Matthew S. Berzins
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Flip-flop having logic state retention during a power down mode and...
- Patent number 7,583,121
- Issue date Sep 1, 2009
- FREESCALE SEMICONDUCTOR, INC.
- Matthew S. Berzins
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Circuit and method for rapid power up of a differential output driver
- Patent number 7,394,293
- Issue date Jul 1, 2008
- Cypress Semiconductor Corp.
- Jeffrey Waldrip
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Circuit and method for CMOS voltage level translation
- Patent number 7,239,178
- Issue date Jul 3, 2007
- Cypress Semiconductor Corp.
- Charles A. Cornell
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Low duty cycle distortion differential to CMOS translator
- Patent number 7,176,720
- Issue date Feb 13, 2007
- Cypress Semiconductor Corp.
- Stephen M. Prather
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method and circuit for translating a differential signal to complem...
- Patent number 7,173,453
- Issue date Feb 6, 2007
- Cypress Semiconductor Corp.
- Stephen M. Prather
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
ZERO DIFFUSION BREAK
- Publication number 20230161940
- Publication date May 25, 2023
- Samsung Electronics Co., Ltd.
- Andrew Paul HOOVER
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LOW POWER INTEGRATED CLOCK GATING SYSTEM AND METHOD
- Publication number 20200295758
- Publication date Sep 17, 2020
- Samsung Electronics Co., Ltd.
- Matthew BERZINS
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
NOVEL METHOD FOR REDUCING POWER CONSUMPTION IN SCANNABLE FLIP-FLOPS...
- Publication number 20200292617
- Publication date Sep 17, 2020
- Samsung Electronics Co., Ltd.
- Matthew BERZINS
- G01 - MEASURING TESTING
Information Patent Application
LOW-POWER LOW-SETUP INTEGRATED CLOCK GATING CELL WITH COMPLEX ENABL...
- Publication number 20200204180
- Publication date Jun 25, 2020
- Samsung Electronics Co., Ltd.
- Matthew BERZINS
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
LAYOUT CONNECTION ISOLATION TECHNIQUE FOR IMPROVING IMMUNITY TO JIT...
- Publication number 20200020678
- Publication date Jan 16, 2020
- Samsung Electronics Co., Ltd.
- Matthew BERZINS
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
POWER GRID AND STANDARD CELL CO-DESIGN STRUCTURE AND METHODS THEREOF
- Publication number 20190385999
- Publication date Dec 19, 2019
- Samsung Electronics Co., Ltd.
- Matthew BERZINS
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM AND METHOD FOR IMPROVING SCAN HOLD-TIME VIOLATION AND LOW VO...
- Publication number 20190221255
- Publication date Jul 18, 2019
- Samsung Electronics Co., Ltd.
- Matthew BERZINS
- G11 - INFORMATION STORAGE
Information Patent Application
SYSTEM AND METHOD FOR IMPROVING SCAN HOLD-TIME VIOLATION AND LOW VO...
- Publication number 20180342287
- Publication date Nov 29, 2018
- Samsung Electronics Co., Ltd.
- Matthew BERZINS
- G11 - INFORMATION STORAGE
Information Patent Application
SYSTEM AND METHOD FOR REDUCING POWER CONSUMPTION IN SCANNABLE CIRCUIT
- Publication number 20180340979
- Publication date Nov 29, 2018
- Samsung Electronics Co., Ltd.
- Matthew BERZINS
- G01 - MEASURING TESTING
Information Patent Application
LOW POWER INTEGRATED CLOCK GATING CELL USING CONTROLLED INVERTED CLOCK
- Publication number 20180287610
- Publication date Oct 4, 2018
- Samsung Electronics Co., Ltd.
- James Jung LIM
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
POWER RAIL FOR STANDARD CELL BLOCK
- Publication number 20180269152
- Publication date Sep 20, 2018
- Samsung Electronics Co., Ltd.
- Rwik Sengupta
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
USING DEEP SUB-MICRON STRESS EFFECTS AND PROXIMITY EFFECTS TO CREAT...
- Publication number 20170337320
- Publication date Nov 23, 2017
- Matthew BERZINS
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTI-BIT FLIP-FLOPS
- Publication number 20170292993
- Publication date Oct 12, 2017
- Samsung Electronics Co., Ltd.
- DOO-SEOK YOON
- G01 - MEASURING TESTING
Information Patent Application
LOW POWER INTEGRATED CLOCK GATING CELL WITH INTERNAL CONTROL SIGNAL
- Publication number 20170201241
- Publication date Jul 13, 2017
- James Jung LIM
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
HIGH SPEED DOMINO-BASED FLIP FLOP
- Publication number 20170077908
- Publication date Mar 16, 2017
- Matthew BERZINS
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
SEMICONDUCTOR CIRCUIT INCLUDING FLIP-FLOP
- Publication number 20170070214
- Publication date Mar 9, 2017
- Samsung Electronics Co., Ltd.
- SAN-HA KIM
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
NOVEL LOW POWER MINIMAL DISRUPTIVE METHOD TO IMPLEMENT LARGE QUANTI...
- Publication number 20160117434
- Publication date Apr 28, 2016
- Brian MILLAR
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTEGRATED CLOCK GATER (ICG) USING CLOCK CASCODE COMPLIMENTARY SWIT...
- Publication number 20160049930
- Publication date Feb 18, 2016
- Matthew S. Berzins
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
LOW POWER TOGGLE LATCH-BASED FLIP-FLOP INCLUDING INTEGRATED CLOCK G...
- Publication number 20150200652
- Publication date Jul 16, 2015
- Samsung Electronics Co., Ltd.
- Matthew BERZINS
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
INTEGRATED CLOCK GATER (ICG) USING CLOCK CASCODE COMPLIMENTARY SWIT...
- Publication number 20150145577
- Publication date May 28, 2015
- Matthew S. Berzins
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
FLIP-FLOP WITH ZERO-DELAY BYPASS MUX
- Publication number 20150036447
- Publication date Feb 5, 2015
- Christina WELLS
- G11 - INFORMATION STORAGE
Information Patent Application
INTEGRATED CLOCK GATER (ICG) USING CLOCK CASCODE COMPLIMENTARY SWIT...
- Publication number 20140266396
- Publication date Sep 18, 2014
- Matthew S. Berzins
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
CIRCUITRY AND METHOD FOR BUFFERING A POWER MODE CONTROL SIGNAL
- Publication number 20090295467
- Publication date Dec 3, 2009
- Matthew S. Berzins
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
FLIP-FLOP HAVING LOGIC STATE RETENTION DURING A POWER DOWN MODE AND...
- Publication number 20090058485
- Publication date Mar 5, 2009
- Matthew S. Berzins
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
PULSED STATE RETENTION POWER GATING FLIP-FLOP
- Publication number 20080315932
- Publication date Dec 25, 2008
- Samuel J. Tower
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Method and circuit for translating a differential signal to complme...
- Publication number 20050134314
- Publication date Jun 23, 2005
- Stephen M. Prather
- H03 - BASIC ELECTRONIC CIRCUITRY

Matthew BERZINS

Person

Patents Grantslast 30 patents

Method for reducing power consumption in scannable flip-flops witho...

Low-power low-setup integrated clock gating cell with complex enabl...

Low power integrated clock gating system and method

Power rail for standard cell block

Power grid and standard cell co-design structure and methods thereof

System and method for improving scan hold-time violation and low vo...

Layout connection isolation technique for improving immunity to jit...

High speed domino-based flip flop

Dynamic flip flop having data independent P-stack feedback

Multi-bit flip-flops

Low power integrated clock gating cell using controlled inverted clock

System and method for improving scan hold-time violation and low vo...

Using deep sub-micron stress effects and proximity effects to creat...

Semiconductor circuit including flip-flop

Flip-flop with zero-delay bypass mux

Low power minimal disruptive method to implement large quantity pus...

Low power integrated clock gating cell with internal control signal

Apparatus for low power high speed integrated clock gating cell

Integrated clock gater (ICG) using clock cascode complimentary swit...

Low power toggle latch-based flip-flop including integrated clock g...

Integrated clock gater (ICG) using clock cascode complimentary swit...

Integrated clock gater (ICG) using clock cascode complimentary swit...

Pulsed state retention power gating flip-flop

Linearized digital phase-locked loop method for maintaining end of...

Circuitry and method for buffering a power mode control signal

Flip-flop having logic state retention during a power down mode and...

Circuit and method for rapid power up of a differential output driver

Circuit and method for CMOS voltage level translation

Low duty cycle distortion differential to CMOS translator

Method and circuit for translating a differential signal to complem...

Patents Applicationslast 30 patents

ZERO DIFFUSION BREAK

LOW POWER INTEGRATED CLOCK GATING SYSTEM AND METHOD

NOVEL METHOD FOR REDUCING POWER CONSUMPTION IN SCANNABLE FLIP-FLOPS...

LOW-POWER LOW-SETUP INTEGRATED CLOCK GATING CELL WITH COMPLEX ENABL...

LAYOUT CONNECTION ISOLATION TECHNIQUE FOR IMPROVING IMMUNITY TO JIT...

POWER GRID AND STANDARD CELL CO-DESIGN STRUCTURE AND METHODS THEREOF

SYSTEM AND METHOD FOR IMPROVING SCAN HOLD-TIME VIOLATION AND LOW VO...

SYSTEM AND METHOD FOR IMPROVING SCAN HOLD-TIME VIOLATION AND LOW VO...

SYSTEM AND METHOD FOR REDUCING POWER CONSUMPTION IN SCANNABLE CIRCUIT

LOW POWER INTEGRATED CLOCK GATING CELL USING CONTROLLED INVERTED CLOCK

POWER RAIL FOR STANDARD CELL BLOCK

USING DEEP SUB-MICRON STRESS EFFECTS AND PROXIMITY EFFECTS TO CREAT...

MULTI-BIT FLIP-FLOPS

LOW POWER INTEGRATED CLOCK GATING CELL WITH INTERNAL CONTROL SIGNAL

HIGH SPEED DOMINO-BASED FLIP FLOP

SEMICONDUCTOR CIRCUIT INCLUDING FLIP-FLOP

NOVEL LOW POWER MINIMAL DISRUPTIVE METHOD TO IMPLEMENT LARGE QUANTI...

INTEGRATED CLOCK GATER (ICG) USING CLOCK CASCODE COMPLIMENTARY SWIT...

LOW POWER TOGGLE LATCH-BASED FLIP-FLOP INCLUDING INTEGRATED CLOCK G...

INTEGRATED CLOCK GATER (ICG) USING CLOCK CASCODE COMPLIMENTARY SWIT...

FLIP-FLOP WITH ZERO-DELAY BYPASS MUX

INTEGRATED CLOCK GATER (ICG) USING CLOCK CASCODE COMPLIMENTARY SWIT...

CIRCUITRY AND METHOD FOR BUFFERING A POWER MODE CONTROL SIGNAL

FLIP-FLOP HAVING LOGIC STATE RETENTION DURING A POWER DOWN MODE AND...

PULSED STATE RETENTION POWER GATING FLIP-FLOP

Method and circuit for translating a differential signal to complme...