Matthew Haycock

Person

Beaverton, OR, US

People

Patents Grantslast 30 patents

Information Patent Grant
Integrated circuit passive signal distribution
- Patent number 8,571,513
- Issue date Oct 29, 2013
- Intel Corporation
- Frank O'Mahony
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Integrated circuit passive signal distribution
- Patent number 8,213,894
- Issue date Jul 3, 2012
- Intel Corporation
- Frank O'Mahony
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Pulse amplitude modulated system with reduced intersymbol interference
- Patent number 7,653,165
- Issue date Jan 26, 2010
- Intel Corporation
- Bryan K. Casper
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Pulse amplitude modulated system with reduced intersymbol interference
- Patent number 7,391,834
- Issue date Jun 24, 2008
- Intel Corporation
- Bryan K. Casper
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Digital bus synchronizer for generating read reset signal
- Patent number 7,328,361
- Issue date Feb 5, 2008
- Intel Corporation
- Matthew B. Haycock
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Simultaneous bidirectional port with synchronization circuit to syn...
- Patent number 7,222,208
- Issue date May 22, 2007
- Intel Corporation
- Matthew B. Haycock
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Simultaneous transmission and reception of signals in different fre...
- Patent number 7,177,288
- Issue date Feb 13, 2007
- Intel Corporation
- Stephen R. Mooney
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
On-chip observability buffer to observer bus traffic
- Patent number 7,171,510
- Issue date Jan 30, 2007
- Intel Corporation
- Matthew B. Haycock
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and unit for deskewing signals
- Patent number 7,120,838
- Issue date Oct 10, 2006
- Intel Corporation
- Bryan K. Casper
- G11 - INFORMATION STORAGE
Information Patent Grant
Digital bus synchronizer for generating read reset signal
- Patent number 6,901,526
- Issue date May 31, 2005
- Intel Corporation
- Matthew B. Haycock
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Low power NRZ interconnect for pulsed signaling
- Patent number 6,894,536
- Issue date May 17, 2005
- Intel Corporation
- Aaron K. Martin
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Systems for interchip communication
- Patent number 6,847,617
- Issue date Jan 25, 2005
- Intel Corporation
- Shekhar Y Borkar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory pass-band signaling
- Patent number 6,845,424
- Issue date Jan 18, 2005
- Intel Corporation
- Bryan K. Casper
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Bidirectional port with clock channel used for synchronization
- Patent number 6,803,790
- Issue date Oct 12, 2004
- Intel Corporation
- Matthew B. Haycock
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Bidirectional port with clock channel used for synchronization
- Patent number 6,791,356
- Issue date Sep 14, 2004
- Intel Corporation
- Matthew B. Haycock
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated circuit stubs in a point-to-point system
- Patent number 6,747,474
- Issue date Jun 8, 2004
- Intel Corporation
- Shekhar Y. Borkar
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Synchronous clock generator for integrated circuits
- Patent number 6,741,107
- Issue date May 25, 2004
- Intel Corporation
- Shekhar Y. Borkar
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method and apparatus for removing and installing a computer system...
- Patent number 6,718,416
- Issue date Apr 6, 2004
- Intel Corporation
- Keith M. Self
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Voltage margin testing of a transmission line analog signal using a...
- Patent number 6,653,893
- Issue date Nov 25, 2003
- Intel Corporation
- Bryan K. Casper
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Apparatus for testing simultaneous bi-directional I/O circuits
- Patent number 6,639,426
- Issue date Oct 28, 2003
- Intel Corporation
- Matthew B. Haycock
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Current mode bidirectional port with data channel used for synchron...
- Patent number 6,597,198
- Issue date Jul 22, 2003
- Intel Corporation
- Matthew B. Haycock
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Transition reduction encoder using current and last bit sets
- Patent number 6,538,584
- Issue date Mar 25, 2003
- Intel Corporation
- Shekhar Y. Borkar
- G11 - INFORMATION STORAGE
Information Patent Grant
Receiver deskewing of multiple source synchronous bits from a paral...
- Patent number 6,536,025
- Issue date Mar 18, 2003
- Intel Corporation
- Joseph T. Kennedy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Voltage mode bidirectional port with data channel used for synchron...
- Patent number 6,529,037
- Issue date Mar 4, 2003
- Intel Corporation
- Matthew B. Haycock
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Rail-to-rail input clocked amplifier
- Patent number 6,441,649
- Issue date Aug 27, 2002
- Intel Corporation
- Aaron K. Martin
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Using a timing strobe for synchronization and validation in a digit...
- Patent number 6,437,601
- Issue date Aug 20, 2002
- Intel Corporation
- Shekhar Y. Borkar
- G11 - INFORMATION STORAGE
Information Patent Grant
Biased control loop circuit for setting impedance of output driver
- Patent number 6,424,175
- Issue date Jul 23, 2002
- Intel Corporation
- Sriram R. Vangal
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Symmetric, voltage-controlled CMOS delay cell with closed-loop repl...
- Patent number 6,377,103
- Issue date Apr 23, 2002
- Intel Corporation
- Stephen R. Mooney
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Data and strobe repeater having a frequency control unit to re-time...
- Patent number 6,373,289
- Issue date Apr 16, 2002
- Intel Corporation
- Aaron K. Martin
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Apparatus and methods for testing simultaneous bi-directional I/O c...
- Patent number 6,348,811
- Issue date Feb 19, 2002
- Intel Corporation
- Matthew B. Haycock
- H04 - ELECTRIC COMMUNICATION TECHNIQUE

Patents Applicationslast 30 patents

Information Patent Application
INTEGRATED CIRCUIT PASSIVE SIGNAL DISTRIBUTION
- Publication number 20120281323
- Publication date Nov 8, 2012
- Frank O'Mahony
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
ERROR MANAGEMENT ACROSS HARDWARE AND SOFTWARE LAYERS
- Publication number 20120221884
- Publication date Aug 30, 2012
- Nicholas P. Carter
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Pulse amplitude modulated system with reduced intersymbol interference
- Publication number 20080181331
- Publication date Jul 31, 2008
- Intel Corporation
- Bryan K. Casper
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Integrated circuit passive signal distribution
- Publication number 20070153445
- Publication date Jul 5, 2007
- Intel Corporation
- Frank O'Mahony
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Systems for interchip communication
- Publication number 20060110952
- Publication date May 25, 2006
- Shekhar Y. Borkar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Digital bus synchronizer for generating read reset signal
- Publication number 20050248367
- Publication date Nov 10, 2005
- Intel Corporation
- Matthew B. Haycock
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEMS FOR INTERCHIP COMMUNICATION
- Publication number 20040225778
- Publication date Nov 11, 2004
- Shekhar Y. Borkar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Bidirectional port with clock channel used for synchronization
- Publication number 20040080338
- Publication date Apr 29, 2004
- Matthew B. Haycock
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Pulse amplitude modulated system with reduced intersymbol interference
- Publication number 20040062319
- Publication date Apr 1, 2004
- Intel Corporation
- Bryan K. Casper
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Method and unit for deskewing signals
- Publication number 20030188234
- Publication date Oct 2, 2003
- Intel Corporation
- Bryan K. Casper
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Memory pass-band signaling
- Publication number 20030145162
- Publication date Jul 31, 2003
- Intel Corporation
- Bryan K. Casper
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Low power NRZ interconnect for pulsed signaling
- Publication number 20030107411
- Publication date Jun 12, 2003
- Intel Corporation
- Aaron K. Martin
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Simultaneous bi-directional channel separation
- Publication number 20030101306
- Publication date May 29, 2003
- Stephen R. Mooney
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
CURRENT MODE BIDIRECTIONAL PORT WITH DATA CHANNEL USED FOR SYNCHRON...
- Publication number 20030067325
- Publication date Apr 10, 2003
- Intel Corporation
- Matthew B. Haycock
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Method and apparatus for realigning bits on a parallel bus
- Publication number 20030061527
- Publication date Mar 27, 2003
- Intel Corporation
- Matthew B. Haycock
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
VOLTAGE MODE BIDIRECTIONAL PORT WITH DATA CHANNEL USED FOR SYNCHRON...
- Publication number 20030048113
- Publication date Mar 13, 2003
- Intel Corporation
- Matthew B. Haycock
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Bidirectional port with clock channel used for synchronization
- Publication number 20030001618
- Publication date Jan 2, 2003
- Matthew B. Haycock
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Voltage margin testing of a transmission line analog signal using a...
- Publication number 20030001667
- Publication date Jan 2, 2003
- Bryan K. Casper
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Receiver deskewing of multiple source synchronous bits from a paral...
- Publication number 20020170024
- Publication date Nov 14, 2002
- Joseph T. Kennedy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Encoded bits over interconnects
- Publication number 20020130794
- Publication date Sep 19, 2002
- Shekhar Y. Borkar
- G11 - INFORMATION STORAGE
Information Patent Application
Synchronous clock generator for integrated circuits
- Publication number 20020125925
- Publication date Sep 12, 2002
- Shekhar Y. Borkar
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Integrated circuit stubs in a point-to-point system
- Publication number 20020117745
- Publication date Aug 29, 2002
- Shekhar Y. Borkar
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Observability buffer
- Publication number 20020095622
- Publication date Jul 18, 2002
- Matthew B. Haycock
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
RAIL-TO-RAIL INPUT CLOCKED AMPLIFIER
- Publication number 20020084838
- Publication date Jul 4, 2002
- Aaron K. Martin
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
USING A TIMING STROBE FOR SYNCHRONIZATION AND VALIDATION IN A DIGIT...
- Publication number 20020079928
- Publication date Jun 27, 2002
- Shekhar Y. Borkar
- G11 - INFORMATION STORAGE
Information Patent Application
Apparatus and methods for testing simultaneous bi-directional I/O c...
- Publication number 20020079926
- Publication date Jun 27, 2002
- Intel Corporation
- Matthew B. Haycock
- H04 - ELECTRIC COMMUNICATION TECHNIQUE

Matthew Haycock

Person

Patents Grantslast 30 patents

Integrated circuit passive signal distribution

Integrated circuit passive signal distribution

Pulse amplitude modulated system with reduced intersymbol interference

Pulse amplitude modulated system with reduced intersymbol interference

Digital bus synchronizer for generating read reset signal

Simultaneous bidirectional port with synchronization circuit to syn...

Simultaneous transmission and reception of signals in different fre...

On-chip observability buffer to observer bus traffic

Method and unit for deskewing signals

Digital bus synchronizer for generating read reset signal

Low power NRZ interconnect for pulsed signaling

Systems for interchip communication

Memory pass-band signaling

Bidirectional port with clock channel used for synchronization

Bidirectional port with clock channel used for synchronization

Integrated circuit stubs in a point-to-point system

Synchronous clock generator for integrated circuits

Method and apparatus for removing and installing a computer system...

Voltage margin testing of a transmission line analog signal using a...

Apparatus for testing simultaneous bi-directional I/O circuits

Current mode bidirectional port with data channel used for synchron...

Transition reduction encoder using current and last bit sets

Receiver deskewing of multiple source synchronous bits from a paral...

Voltage mode bidirectional port with data channel used for synchron...

Rail-to-rail input clocked amplifier

Using a timing strobe for synchronization and validation in a digit...

Biased control loop circuit for setting impedance of output driver

Symmetric, voltage-controlled CMOS delay cell with closed-loop repl...

Data and strobe repeater having a frequency control unit to re-time...

Apparatus and methods for testing simultaneous bi-directional I/O c...

Patents Applicationslast 30 patents

INTEGRATED CIRCUIT PASSIVE SIGNAL DISTRIBUTION

ERROR MANAGEMENT ACROSS HARDWARE AND SOFTWARE LAYERS

Pulse amplitude modulated system with reduced intersymbol interference

Integrated circuit passive signal distribution

Systems for interchip communication

Digital bus synchronizer for generating read reset signal

SYSTEMS FOR INTERCHIP COMMUNICATION

Bidirectional port with clock channel used for synchronization

Pulse amplitude modulated system with reduced intersymbol interference

Method and unit for deskewing signals

Memory pass-band signaling

Low power NRZ interconnect for pulsed signaling

Simultaneous bi-directional channel separation

CURRENT MODE BIDIRECTIONAL PORT WITH DATA CHANNEL USED FOR SYNCHRON...

Method and apparatus for realigning bits on a parallel bus

VOLTAGE MODE BIDIRECTIONAL PORT WITH DATA CHANNEL USED FOR SYNCHRON...

Bidirectional port with clock channel used for synchronization

Voltage margin testing of a transmission line analog signal using a...

Receiver deskewing of multiple source synchronous bits from a paral...

Encoded bits over interconnects

Synchronous clock generator for integrated circuits

Integrated circuit stubs in a point-to-point system

Observability buffer

RAIL-TO-RAIL INPUT CLOCKED AMPLIFIER

USING A TIMING STROBE FOR SYNCHRONIZATION AND VALIDATION IN A DIGIT...

Apparatus and methods for testing simultaneous bi-directional I/O c...