Matthew L. Balzan

Person

Roanoke, VA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Heterojunction confined channel FET
- Patent number 4,994,868
- Issue date Feb 19, 1991
- ITT Corporation
- Arthur E. Geissberger
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Self-aligned gate realignment employing planarizing overetch
- Patent number 4,965,218
- Issue date Oct 23, 1990
- ITT Corporation
- Arthur E. Geissberger
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
GaAs FET manufacturing process employing channel confining layers
- Patent number 4,962,050
- Issue date Oct 9, 1990
- ITT Corporation
- Arthur E. Geissberger
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of making sagfets on buffer layers
- Patent number 4,948,752
- Issue date Aug 14, 1990
- ITT Corporation
- Arthur E. Geissberger
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Sagfet with buffer layers
- Patent number 4,918,493
- Issue date Apr 17, 1990
- ITT Corporation
- Arthur E. Geissberger
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Self-aligned refractory gate process with self-limiting undercut of...
- Patent number 4,849,376
- Issue date Jul 18, 1989
- ITT A Division of ITT Corporation Gallium Arsenide Technology Center
- Matthew L. Balzan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Self-aligned gate FET process using undercut etch mask
- Patent number 4,847,212
- Issue date Jul 11, 1989
- ITT Gallium Arsenide Technology Center
- Matthew L. Balzan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of making self-aligned GaAs devices having TiWN.sub.x gate/i...
- Patent number 4,782,032
- Issue date Nov 1, 1988
- ITT Gallium Arsenide Technology Center, a division of ITT Corporation
- Arthur E. Geissberger
- H01 - BASIC ELECTRIC ELEMENTS

Matthew L. Balzan

Person

Patents Grantslast 30 patents

Heterojunction confined channel FET

Self-aligned gate realignment employing planarizing overetch

GaAs FET manufacturing process employing channel confining layers

Method of making sagfets on buffer layers

Sagfet with buffer layers

Self-aligned refractory gate process with self-limiting undercut of...

Self-aligned gate FET process using undercut etch mask

Method of making self-aligned GaAs devices having TiWN.sub.x gate/i...