Mei Luo

Person

San Jose, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Apparatus and method for polarity tap control
- Patent number 9,094,239
- Issue date Jul 28, 2015
- Altera Corporation
- Mei Luo
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Clock duty cycle calibration circuitry
- Patent number 9,030,244
- Issue date May 12, 2015
- Altera Corporation
- Mei Luo
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Apparatus and method for common mode tracking in DFE adaptation
- Patent number 8,831,084
- Issue date Sep 9, 2014
- Altera Corporation
- Wing Liu
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Techniques for decision feedback equalization that reduce variation...
- Patent number 8,416,898
- Issue date Apr 9, 2013
- Altera Corporation
- Mei Luo
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Duty cycle correction circuitry
- Patent number 7,999,588
- Issue date Aug 16, 2011
- Altera Corporation
- Mingde Pan
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Versatile common-mode driver methods and apparatus
- Patent number 7,855,576
- Issue date Dec 21, 2010
- Altera Corporation
- Mei Luo
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Dynamically-adjustable differential output drivers
- Patent number 7,675,326
- Issue date Mar 9, 2010
- Altera Corporation
- Mei Luo
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
High-speed serial data transmitter architecture
- Patent number 7,557,615
- Issue date Jul 7, 2009
- Altera Corporation
- Thungoc M. Tran
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
High-speed level-shifting circuit
- Patent number 7,521,964
- Issue date Apr 21, 2009
- Altera Corporation
- Mei Luo
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Dynamically-adjustable differential output drivers
- Patent number 7,397,270
- Issue date Jul 8, 2008
- Altera Corporation
- Mei Luo
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
High-speed serial data transmitter architecture
- Patent number 7,355,449
- Issue date Apr 8, 2008
- Altera Corporation
- Thungoc Tran
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Dynamically adjustable termination impedance control techniques
- Patent number 7,176,710
- Issue date Feb 13, 2007
- Altera Corporation
- Mei Luo
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Dynamically-adjustable differential output drivers
- Patent number 6,943,588
- Issue date Sep 13, 2005
- Altera Corporation
- Mei Luo
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Dynamically adjustable termination impedance control techniques
- Patent number 6,888,370
- Issue date May 3, 2005
- Altera Corporation
- Mei Luo
- H04 - ELECTRIC COMMUNICATION TECHNIQUE

Person

Patents Grantslast 30 patents

Apparatus and method for polarity tap control

Clock duty cycle calibration circuitry

Apparatus and method for common mode tracking in DFE adaptation

Techniques for decision feedback equalization that reduce variation...

Duty cycle correction circuitry

Versatile common-mode driver methods and apparatus

Dynamically-adjustable differential output drivers

High-speed serial data transmitter architecture

High-speed level-shifting circuit

Dynamically-adjustable differential output drivers

High-speed serial data transmitter architecture

Dynamically adjustable termination impedance control techniques

Dynamically-adjustable differential output drivers

Dynamically adjustable termination impedance control techniques