Michael A. Guillorn

Person

Cold Springs, NY, US

People

Patents Grantslast 30 patents

Information Patent Grant
Nanosheet field effect transistors with partial inside spacers
- Patent number 11,342,446
- Issue date May 24, 2022
- Tessera, Inc.
- Michael A. Guillorn
- B82 - NANO-TECHNOLOGY
Information Patent Grant
Electrical mask validation
- Patent number 11,288,429
- Issue date Mar 29, 2022
- International Business Machines Corporation
- Daniel Corliss
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Gate-all-around field effect transistor having multiple threshold v...
- Patent number 11,245,020
- Issue date Feb 8, 2022
- International Business Machines Corporation
- Ruqiang Bao
- B82 - NANO-TECHNOLOGY
Information Patent Grant
Trigate device with full silicided epi-less source/drain for high d...
- Patent number 11,075,265
- Issue date Jul 27, 2021
- International Business Machines Corporation
- Michael A. Guillorn
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Sacrificial layer for channel surface retention and inner spacer fo...
- Patent number 11,069,775
- Issue date Jul 20, 2021
- International Business Machines Corporation
- Josephine B. Chang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Atomic layer deposition sealing integration for nanosheet complemen...
- Patent number 11,004,678
- Issue date May 11, 2021
- International Business Machines Corporation
- Bruce B. Doris
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Field effect transistor structures
- Patent number 11,004,933
- Issue date May 11, 2021
- Tessera, Inc.
- Josephine B. Chang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Automatic generation of via patterns with coordinate-based recurren...
- Patent number 10,990,747
- Issue date Apr 27, 2021
- International Business Machines Corporation
- Jing Sha
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Reducing chemoepitaxy directed self-assembled defects
- Patent number 10,949,601
- Issue date Mar 16, 2021
- International Business Machines Corporation
- Michael A. Guillorn
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Semiconductor structure for optical validation
- Patent number 10,921,715
- Issue date Feb 16, 2021
- International Business Machines Corporation
- Daniel Corliss
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Nanosheet and nanowire MOSFET with sharp source/drain junction
- Patent number 10,840,381
- Issue date Nov 17, 2020
- International Business Machines Corporation
- Josephine B. Chang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
High density programmable e-fuse co-integrated with vertical FETs
- Patent number 10,804,278
- Issue date Oct 13, 2020
- ELPIS TECHNOLOGIES INC.
- Karthik Balakrishnan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Dielectric isolation and SiGe channel formation for integration in...
- Patent number 10,741,641
- Issue date Aug 11, 2020
- International Business Machines Corporation
- Michael A. Guillorn
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Generative adversarial networks for generating physical design layo...
- Patent number 10,706,200
- Issue date Jul 7, 2020
- International Business Machines Corporation
- Jing Sha
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Generative adversarial networks for generating physical design layo...
- Patent number 10,699,055
- Issue date Jun 30, 2020
- International Business Machines Corporation
- Jing Sha
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Sacrificial layer for channel surface retention and inner spacer fo...
- Patent number 10,680,061
- Issue date Jun 9, 2020
- International Business Machines Corporation
- Josephine B. Chang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Nanowire with sacrificial top wire
- Patent number 10,658,461
- Issue date May 19, 2020
- Tessera, Inc.
- Josephine B. Chang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Electrical mask validation
- Patent number 10,650,111
- Issue date May 12, 2020
- International Business Machines Corporation
- Daniel Corliss
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Classification and localization of hotspots in integrated physical...
- Patent number 10,621,302
- Issue date Apr 14, 2020
- International Business Machines Corporation
- Jing Sha
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Coordinates-based variational autoencoder for generating synthetic...
- Patent number 10,621,301
- Issue date Apr 14, 2020
- International Business Machines Corporation
- Jing Sha
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Semiconductor device including wrap around contact and method of fo...
- Patent number 10,615,281
- Issue date Apr 7, 2020
- International Business Machines Corporation
- Michael A. Guillorn
- B82 - NANO-TECHNOLOGY
Information Patent Grant
Coordinates-based generative adversarial networks for generating sy...
- Patent number 10,606,975
- Issue date Mar 31, 2020
- International Business Machines Corporation
- Jing Sha
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and recording medium of reducing chemoepitaxy directed self-...
- Patent number 10,606,980
- Issue date Mar 31, 2020
- International Business Machines Corporation
- Michael A. Guillorn
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Automatic generation of via patterns with coordinate-based recurren...
- Patent number 10,599,807
- Issue date Mar 24, 2020
- International Business Machines Corporation
- Jing Sha
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Chemoepitaxy etch trim using a self aligned hard mask for metal lin...
- Patent number 10,600,680
- Issue date Mar 24, 2020
- International Business Machines Corporation
- Markus Brink
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
Generating synthetic layout patterns by feedforward neural network...
- Patent number 10,592,635
- Issue date Mar 17, 2020
- International Business Machines Corporation
- Jing Sha
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Gate-all-around field effect transistor having multiple threshold v...
- Patent number 10,586,854
- Issue date Mar 10, 2020
- International Business Machines Corporation
- Ruqiang Bao
- B82 - NANO-TECHNOLOGY
Information Patent Grant
Preventing threshold voltage variability in stacked nanosheets
- Patent number 10,580,858
- Issue date Mar 3, 2020
- International Business Machines Corporation
- Michael A. Guillorn
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Sacrificial layer for channel surface retention and inner spacer fo...
- Patent number 10,573,714
- Issue date Feb 25, 2020
- International Business Machines Corporation
- Josephine B. Chang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Nanosheet field effect transistors with partial inside spacers
- Patent number 10,559,670
- Issue date Feb 11, 2020
- International Business Machines Corporation
- Michael A. Guillorn
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
NANOSHEET FIELD EFFECT TRANSISTORS WITH PARTIAL INSIDE SPACERS
- Publication number 20220320316
- Publication date Oct 6, 2022
- TESSERA LLC
- Michael A. Guillorn
- B82 - NANO-TECHNOLOGY
Information Patent Application
FIELD EFFECT TRANSISTOR STRUCTURES
- Publication number 20210280674
- Publication date Sep 9, 2021
- Tessera, Inc.
- Josephine B. Chang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
GATE-ALL-AROUND FIELD EFFECT TRANSISTOR HAVING MULTIPLE THRESHOLD V...
- Publication number 20200258995
- Publication date Aug 13, 2020
- International Business Machines Corporation
- Ruqiang Bao
- B82 - NANO-TECHNOLOGY
Information Patent Application
GATE-ALL-AROUND FIELD EFFECT TRANSISTOR HAVING MULTIPLE THRESHOLD V...
- Publication number 20200251568
- Publication date Aug 6, 2020
- International Business Machines Corporation
- Ruqiang Bao
- B82 - NANO-TECHNOLOGY
Information Patent Application
AUTOMATIC GENERATION OF VIA PATTERNS WITH COORDINATE-BASED RECURREN...
- Publication number 20200159983
- Publication date May 21, 2020
- International Business Machines Corporation
- Jing Sha
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ELECTRICAL MASK VALIDATION
- Publication number 20200143098
- Publication date May 7, 2020
- International Business Machines Corporation
- Daniel Corliss
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
REDUCING CHEMOEPITAXY DIRECTED SELF-ASSEMBLED DEFECTS
- Publication number 20200134251
- Publication date Apr 30, 2020
- International Business Machines Corporation
- Michael A. Guillorn
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
NANOSHEET FIELD EFFECT TRANSISTORS WITH PARTIAL INSIDE SPACERS
- Publication number 20200098893
- Publication date Mar 26, 2020
- International Business Machines Corporation
- Michael A. Guillorn
- B82 - NANO-TECHNOLOGY
Information Patent Application
SACRIFICIAL LAYER FOR CHANNEL SURFACE RETENTION AND INNER SPACER FO...
- Publication number 20200091289
- Publication date Mar 19, 2020
- International Business Machines Corporation
- Josephine B. Chang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ATOMIC LAYER DEPOSITION SEALING INTEGRATION FOR NANOSHEET COMPLEMEN...
- Publication number 20200066508
- Publication date Feb 27, 2020
- International Business Machines Corporation
- Bruce B. Doris
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CLASSIFICATION AND LOCALIZATION OF HOTSPOTS IN INTEGRATED PHYSICAL...
- Publication number 20200004918
- Publication date Jan 2, 2020
- International Business Machines Corporation
- Jing Sha
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DIELECTRIC ISOLATION AND SiGe CHANNEL FORMATION FOR INTEGRATION IN...
- Publication number 20190393304
- Publication date Dec 26, 2019
- International Business Machines Corporation
- Michael A. Guillorn
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
COORDINATES-BASED VARIATIONAL AUTOENCODER FOR GENERATING SYNTHETIC...
- Publication number 20190377848
- Publication date Dec 12, 2019
- International Business Machines Corporation
- Jing Sha
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
GENERATIVE ADVERSARIAL NETWORKS FOR GENERATING PHYSICAL DESIGN LAYO...
- Publication number 20190377849
- Publication date Dec 12, 2019
- International Business Machines Corporation
- Jing Sha
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COORDINATES-BASED GENERATIVE ADVERSARIAL NETWORKS FOR GENERATING SY...
- Publication number 20190370431
- Publication date Dec 5, 2019
- International Business Machines Corporation
- Jing Sha
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
AUTOMATIC GENERATION OF VIA PATTERNS WITH COORDINATE-BASED RECURREN...
- Publication number 20190370434
- Publication date Dec 5, 2019
- International Business Machines Corporation
- Jing Sha
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
GENERATING SYNTHETIC LAYOUT PATTERNS BY FEEDFORWARD NEURAL NETWORK...
- Publication number 20190370435
- Publication date Dec 5, 2019
- International Business Machines Corporation
- Jing Sha
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
GENERATIVE ADVERSARIAL NETWORKS FOR GENERATING PHYSICAL DESIGN LAYO...
- Publication number 20190370432
- Publication date Dec 5, 2019
- International Business Machines Corporation
- Jing Sha
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SEMICONDUCTOR STRUCTURE FOR OPTICAL VALIDATION
- Publication number 20190346773
- Publication date Nov 14, 2019
- International Business Machines Corporation
- Daniel Corliss
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HIGH DENSITY PROGRAMMABLE E-FUSE CO-INTEGRATED WITH VERTICAL FETS
- Publication number 20190312044
- Publication date Oct 10, 2019
- International Business Machines Corporation
- Karthik Balakrishnan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MULTIPLE-THRESHOLD NANOSHEET TRANSISTORS
- Publication number 20190252495
- Publication date Aug 15, 2019
- International Business Machines Corporation
- Ruqiang Bao
- B82 - NANO-TECHNOLOGY
Information Patent Application
TRIGATE DEVICE WITH FULL SILICIDED EPI-LESS SOURCE/DRAIN FOR HIGH D...
- Publication number 20190237538
- Publication date Aug 1, 2019
- International Business Machines Corporation
- Michael A. Guillorn
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SACRIFICIAL LAYER FOR CHANNEL SURFACE RETENTION AND INNER SPACER FO...
- Publication number 20190237541
- Publication date Aug 1, 2019
- International Business Machines Corporation
- Josephine B. Chang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
OPTICAL MASK VALIDATION
- Publication number 20190163071
- Publication date May 30, 2019
- International Business Machines Corporation
- Daniel Corliss
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ELECTRICAL MASK VALIDATION
- Publication number 20190163857
- Publication date May 30, 2019
- International Business Machines Corporation
- Daniel Corliss
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CHEMOEPITAXY ETCH TRIM USING A SELF ALIGNED HARD MASK FOR METAL LIN...
- Publication number 20190043754
- Publication date Feb 7, 2019
- International Business Machines Corporation
- Markus Brink
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PREVENTING THRESHOLD VOLTAGE VARIABILITY IN STACKED NANOSHEETS
- Publication number 20190006462
- Publication date Jan 3, 2019
- International Business Machines Corporation
- Michael A. Guillorn
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor Device Including Wrap Around Contact and Method of Fo...
- Publication number 20180374958
- Publication date Dec 27, 2018
- International Business Machines Corporation
- Michael A. Guillorn
- B82 - NANO-TECHNOLOGY
Information Patent Application
INTEGRATING AND ISOLATING NFET AND PFET NANOSHEET TRANSISTORS ON A...
- Publication number 20180374761
- Publication date Dec 27, 2018
- International Business Machines Corporation
- Michael A. Guillorn
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SACRIFICIAL LAYER FOR CHANNEL SURFACE RETENTION AND INNER SPACER FO...
- Publication number 20180366544
- Publication date Dec 20, 2018
- International Business Machines Corporation
- Josephine B. Chang
- H01 - BASIC ELECTRIC ELEMENTS

Michael A. Guillorn

Person

Patents Grantslast 30 patents

Nanosheet field effect transistors with partial inside spacers

Electrical mask validation

Gate-all-around field effect transistor having multiple threshold v...

Trigate device with full silicided epi-less source/drain for high d...

Sacrificial layer for channel surface retention and inner spacer fo...

Atomic layer deposition sealing integration for nanosheet complemen...

Field effect transistor structures

Automatic generation of via patterns with coordinate-based recurren...

Reducing chemoepitaxy directed self-assembled defects

Semiconductor structure for optical validation

Nanosheet and nanowire MOSFET with sharp source/drain junction

High density programmable e-fuse co-integrated with vertical FETs

Dielectric isolation and SiGe channel formation for integration in...

Generative adversarial networks for generating physical design layo...

Generative adversarial networks for generating physical design layo...

Sacrificial layer for channel surface retention and inner spacer fo...

Nanowire with sacrificial top wire

Electrical mask validation

Classification and localization of hotspots in integrated physical...

Coordinates-based variational autoencoder for generating synthetic...

Semiconductor device including wrap around contact and method of fo...

Coordinates-based generative adversarial networks for generating sy...

Method and recording medium of reducing chemoepitaxy directed self-...

Automatic generation of via patterns with coordinate-based recurren...

Chemoepitaxy etch trim using a self aligned hard mask for metal lin...

Generating synthetic layout patterns by feedforward neural network...

Gate-all-around field effect transistor having multiple threshold v...

Preventing threshold voltage variability in stacked nanosheets

Sacrificial layer for channel surface retention and inner spacer fo...

Nanosheet field effect transistors with partial inside spacers

Patents Applicationslast 30 patents

NANOSHEET FIELD EFFECT TRANSISTORS WITH PARTIAL INSIDE SPACERS

FIELD EFFECT TRANSISTOR STRUCTURES

GATE-ALL-AROUND FIELD EFFECT TRANSISTOR HAVING MULTIPLE THRESHOLD V...

GATE-ALL-AROUND FIELD EFFECT TRANSISTOR HAVING MULTIPLE THRESHOLD V...

AUTOMATIC GENERATION OF VIA PATTERNS WITH COORDINATE-BASED RECURREN...

ELECTRICAL MASK VALIDATION

REDUCING CHEMOEPITAXY DIRECTED SELF-ASSEMBLED DEFECTS

NANOSHEET FIELD EFFECT TRANSISTORS WITH PARTIAL INSIDE SPACERS

SACRIFICIAL LAYER FOR CHANNEL SURFACE RETENTION AND INNER SPACER FO...

ATOMIC LAYER DEPOSITION SEALING INTEGRATION FOR NANOSHEET COMPLEMEN...

CLASSIFICATION AND LOCALIZATION OF HOTSPOTS IN INTEGRATED PHYSICAL...

DIELECTRIC ISOLATION AND SiGe CHANNEL FORMATION FOR INTEGRATION IN...

COORDINATES-BASED VARIATIONAL AUTOENCODER FOR GENERATING SYNTHETIC...

GENERATIVE ADVERSARIAL NETWORKS FOR GENERATING PHYSICAL DESIGN LAYO...

COORDINATES-BASED GENERATIVE ADVERSARIAL NETWORKS FOR GENERATING SY...

AUTOMATIC GENERATION OF VIA PATTERNS WITH COORDINATE-BASED RECURREN...

GENERATING SYNTHETIC LAYOUT PATTERNS BY FEEDFORWARD NEURAL NETWORK...

GENERATIVE ADVERSARIAL NETWORKS FOR GENERATING PHYSICAL DESIGN LAYO...

SEMICONDUCTOR STRUCTURE FOR OPTICAL VALIDATION

HIGH DENSITY PROGRAMMABLE E-FUSE CO-INTEGRATED WITH VERTICAL FETS

MULTIPLE-THRESHOLD NANOSHEET TRANSISTORS

TRIGATE DEVICE WITH FULL SILICIDED EPI-LESS SOURCE/DRAIN FOR HIGH D...

SACRIFICIAL LAYER FOR CHANNEL SURFACE RETENTION AND INNER SPACER FO...

OPTICAL MASK VALIDATION

ELECTRICAL MASK VALIDATION

CHEMOEPITAXY ETCH TRIM USING A SELF ALIGNED HARD MASK FOR METAL LIN...

PREVENTING THRESHOLD VOLTAGE VARIABILITY IN STACKED NANOSHEETS

Semiconductor Device Including Wrap Around Contact and Method of Fo...

INTEGRATING AND ISOLATING NFET AND PFET NANOSHEET TRANSISTORS ON A...

SACRIFICIAL LAYER FOR CHANNEL SURFACE RETENTION AND INNER SPACER FO...