Michael Ira Current

Person

San Jose, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Method of forming semiconductor device using high stress cleave plane
- Patent number 12,176,326
- Issue date Dec 24, 2024
- Silicon Genesis Corporation
- Theodore E. Fong
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Three dimensional integrated circuit with lateral connection layer
- Patent number 11,901,351
- Issue date Feb 13, 2024
- Silicon Genesis Corporation
- Michael I. Current
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming semiconductor device using range compensating mat...
- Patent number 11,626,392
- Issue date Apr 11, 2023
- Silicon Genesis Corporation
- Theodore E. Fong
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Three dimensional integrated circuit with lateral connection layer
- Patent number 11,410,984
- Issue date Aug 9, 2022
- Silicon Genesis Corporation
- Michael I. Current
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Three dimensional integrated circuit
- Patent number 10,923,459
- Issue date Feb 16, 2021
- Silicon Genesis Corporation
- Theodore E. Fong
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Limited dose and angle directed beam assisted ALE and ALD processes...
- Patent number 10,923,359
- Issue date Feb 16, 2021
- Thomas E Seidel
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Limited dose atomic layer processes for localizing coatings on non-...
- Patent number 10,896,823
- Issue date Jan 19, 2021
- Thomas E. Seidel
- G01 - MEASURING TESTING
Information Patent Grant
Three dimensional integrated circuit
- Patent number 10,804,252
- Issue date Oct 13, 2020
- Silicon Genesis Corporation
- Theodore E. Fong
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Three dimensional integrated circuit
- Patent number 10,573,627
- Issue date Feb 25, 2020
- Silicon Genesis Corporation
- Theodore E. Fong
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Three dimensional integrated circuit
- Patent number 10,049,915
- Issue date Aug 14, 2018
- SILICON GENESIS CORPORATION
- Theodore E. Fong
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Three dimensional integrated circuit
- Patent number 9,704,835
- Issue date Jul 11, 2017
- SILICON GENESIS CORPORATION
- Theodore E. Fong
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Non-contact etch annealing of strained layers
- Patent number 8,187,377
- Issue date May 29, 2012
- Silicon Genesis Corporation
- Igor J. Malik
- C30 - CRYSTAL GROWTH
Information Patent Grant
Non-contact method and apparatus for measurement of leakage current...
- Patent number 7,642,772
- Issue date Jan 5, 2010
- Ahbee 1, L.P.
- Vladimir Faifer
- G01 - MEASURING TESTING
Information Patent Grant
Non-contact method and apparatus for measurement of leakage current...
- Patent number 7,414,409
- Issue date Aug 19, 2008
- Vladimir Faifer
- G01 - MEASURING TESTING
Information Patent Grant
Non-contact method and apparatus for measurement of sheet resistanc...
- Patent number 7,019,513
- Issue date Mar 28, 2006
- Vladimir Faifer
- G01 - MEASURING TESTING

Patents Applicationslast 30 patents

Information Patent Application
THREE DIMENSIONAL INTEGRATED CIRCUIT WITH INTERCONNECT NETWORK LAYER
- Publication number 20240145459
- Publication date May 2, 2024
- Silicon Genesis Corporation
- Michael I. CURRENT
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD OF FORMING SEMICONDUCTOR DEVICE USING HIGH STRESS CLEAVE PLANE
- Publication number 20230299060
- Publication date Sep 21, 2023
- Silicon Genesis Corporation
- Theodore E. FONG
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
THREE DIMENSIONAL INTEGRATED CIRCUIT WITH LATERAL CONNECTION LAYER
- Publication number 20230215857
- Publication date Jul 6, 2023
- Silicon Genesis Corporation
- Michael I. CURRENT
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
THREE DIMENSIONAL INTEGRATED CIRCUIT
- Publication number 20210242184
- Publication date Aug 5, 2021
- Silicon Genesis Corporation
- Theodore E. FONG
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
LIMITED DOSE AND ANGLE DIRECTED BEAM ASSISTED ALE AND ALD PROCESSES...
- Publication number 20210020452
- Publication date Jan 21, 2021
- Thomas E Seidel
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
THREE DIMENSIONAL INTEGRATED CIRCUIT
- Publication number 20200194409
- Publication date Jun 18, 2020
- Silicon Genesis Corporation
- Theodore E. FONG
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
THREE DIMENSIONAL INTEGRATED CIRCUIT
- Publication number 20200185364
- Publication date Jun 11, 2020
- Silicon Genesis Corporation
- Theodore E. FONG
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
LIMITED DOSE ATOMIC LAYER PROCESSES FOR LOCALIZING COATINGS ON NON-...
- Publication number 20200161140
- Publication date May 21, 2020
- Thomas E. Seidel
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
THREE DIMENSIONAL INTEGRATED CIRCUIT
- Publication number 20180350785
- Publication date Dec 6, 2018
- Silicon Genesis Corporation
- Theodore E. FONG
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
THREE DIMENSIONAL INTEGRATED CIRCUIT
- Publication number 20180175008
- Publication date Jun 21, 2018
- Silicon Genesis Corporation
- Theodore E. FONG
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
THREE DIMENSIONAL INTEGRATED CIRCUIT
- Publication number 20180082989
- Publication date Mar 22, 2018
- Silicon Genesis Corporation
- Theodore E. FONG
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
THREE DIMENSIONAL INTEGRATED CIRCUIT
- Publication number 20170301657
- Publication date Oct 19, 2017
- Silicon Genesis Corporation
- Theodore E. FONG
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SILICON DOPING SOURCE FILMS BY ALD DEPOSITION
- Publication number 20160379828
- Publication date Dec 29, 2016
- Anil U. Mane
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Application
THREE DIMENSIONAL INTEGRATED CIRCUIT
- Publication number 20160204088
- Publication date Jul 14, 2016
- Silicon Genesis Corporation
- Theodore E. FONG
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Non-contact etch annealing of strained layers
- Publication number 20040067644
- Publication date Apr 8, 2004
- Igor J. Malik
- C30 - CRYSTAL GROWTH

Michael Ira Current

Person

Patents Grantslast 30 patents

Method of forming semiconductor device using high stress cleave plane

Three dimensional integrated circuit with lateral connection layer

Method of forming semiconductor device using range compensating mat...

Three dimensional integrated circuit with lateral connection layer

Three dimensional integrated circuit

Limited dose and angle directed beam assisted ALE and ALD processes...

Limited dose atomic layer processes for localizing coatings on non-...

Three dimensional integrated circuit

Three dimensional integrated circuit

Three dimensional integrated circuit

Three dimensional integrated circuit

Non-contact etch annealing of strained layers

Non-contact method and apparatus for measurement of leakage current...

Non-contact method and apparatus for measurement of leakage current...

Non-contact method and apparatus for measurement of sheet resistanc...

Patents Applicationslast 30 patents

THREE DIMENSIONAL INTEGRATED CIRCUIT WITH INTERCONNECT NETWORK LAYER

METHOD OF FORMING SEMICONDUCTOR DEVICE USING HIGH STRESS CLEAVE PLANE

THREE DIMENSIONAL INTEGRATED CIRCUIT WITH LATERAL CONNECTION LAYER

THREE DIMENSIONAL INTEGRATED CIRCUIT

LIMITED DOSE AND ANGLE DIRECTED BEAM ASSISTED ALE AND ALD PROCESSES...

THREE DIMENSIONAL INTEGRATED CIRCUIT

THREE DIMENSIONAL INTEGRATED CIRCUIT

LIMITED DOSE ATOMIC LAYER PROCESSES FOR LOCALIZING COATINGS ON NON-...

THREE DIMENSIONAL INTEGRATED CIRCUIT

THREE DIMENSIONAL INTEGRATED CIRCUIT

THREE DIMENSIONAL INTEGRATED CIRCUIT

THREE DIMENSIONAL INTEGRATED CIRCUIT

SILICON DOPING SOURCE FILMS BY ALD DEPOSITION

THREE DIMENSIONAL INTEGRATED CIRCUIT

Non-contact etch annealing of strained layers