Michael K. Ciraula

Person

Austin, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
Staged bitline precharge
- Patent number 11,361,819
- Issue date Jun 14, 2022
- Advanced Micro Devices, Inc.
- Andrew Robison
- G11 - INFORMATION STORAGE
Information Patent Grant
Flexibile interfaces using through-silicon via technology
- Patent number 10,644,826
- Issue date May 5, 2020
- Advanced Micro Devices, Inc.
- John Wuu
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Configuration of multi-die modules with through-silicon vias
- Patent number 10,509,752
- Issue date Dec 17, 2019
- Advanced Micro Devices, Inc.
- Russell Schreiber
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Error injection for assessment of error detection and correction te...
- Patent number 10,452,505
- Issue date Oct 22, 2019
- Advanced Micro Devices, Inc.
- Michael K. Ciraula
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Swizzling in 3D stacked memory
- Patent number 10,303,398
- Issue date May 28, 2019
- Advanced Micro Devices, Inc.
- John Wuu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Predictive multistage comparison for associative memory
- Patent number 9,916,246
- Issue date Mar 13, 2018
- Advanced Micro Devices, Inc.
- Carson Donahue Henrion
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory elements for performing an allocation operation and related...
- Patent number 8,533,396
- Issue date Sep 10, 2013
- Advanced Micro Devices, Inc.
- Michael Ciraula
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Wafer stage storage structure speed testing
- Patent number 7,417,449
- Issue date Aug 26, 2008
- Advanced Micro Devices, Inc.
- Randal L. Posey
- G01 - MEASURING TESTING
Information Patent Grant
Multi-ported register cell with randomly accessible history
- Patent number 7,366,032
- Issue date Apr 29, 2008
- Advanced Micro Devices, Inc.
- Jan-Michael Huber
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory array with global bitline domino read/write scheme
- Patent number 7,355,881
- Issue date Apr 8, 2008
- Advanced Micro Devices, Inc.
- Floyd L. Dankert
- G11 - INFORMATION STORAGE
Information Patent Grant
Decode structure with parallel rotation
- Patent number 7,268,591
- Issue date Sep 11, 2007
- Advanced Micro Devices , Inc.
- Jan-Michael Huber
- G11 - INFORMATION STORAGE
Information Patent Grant
Circular buffer using age vectors
- Patent number 7,080,170
- Issue date Jul 18, 2006
- Advanced Micro Devices, Inc.
- Gerald D. Zuraski, Jr.
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Circular buffer using grouping for find first function
- Patent number 6,873,184
- Issue date Mar 29, 2005
- Advanced Micro Devices, Inc.
- Brian D. McMinn
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Elimination of SOI parasitic bipolar effect
- Patent number 6,150,834
- Issue date Nov 21, 2000
- International Business Machines Corporation
- Michael Kevin Ciraula
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Power-saving dynamic circuit
- Patent number 6,121,796
- Issue date Sep 19, 2000
- International Business Machines Corporation
- Michael Kevin Ciraula
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Circuit having anti-charge share characteristics and method therefore
- Patent number 6,111,434
- Issue date Aug 29, 2000
- International Business Machines Corporation
- Michael Kevin Ciraula
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Conditional restore for RAM based on feedback from a RAM cell to pr...
- Patent number 6,108,255
- Issue date Aug 22, 2000
- International Business Machines Corporation
- Michael Kevin Ciraula
- G11 - INFORMATION STORAGE
Information Patent Grant
Initialization of floating body dynamic circuitry
- Patent number 6,094,071
- Issue date Jul 25, 2000
- International Business Machines Corporation
- Michael Kevin Ciraula
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method and system for load data formatting and improved method for...
- Patent number 6,085,289
- Issue date Jul 4, 2000
- International Business Machines Corporation
- Larry Edward Thatcher
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Conditional restore for SRAM
- Patent number 6,064,616
- Issue date May 16, 2000
- International Business Machines Corporation
- Michael Kevin Ciraula
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory array and method for writing data to memory
- Patent number 6,046,930
- Issue date Apr 4, 2000
- International Business Machines Corporation
- Michael Kevin Ciraula
- G11 - INFORMATION STORAGE
Information Patent Grant
Conditional restore for execution unit
- Patent number 6,025,741
- Issue date Feb 15, 2000
- International Business Machines Corporation
- Michael Kevin Ciraula
- G11 - INFORMATION STORAGE
Information Patent Grant
Translation shadow array adder-decoder circuit for selecting consec...
- Patent number 5,970,512
- Issue date Oct 19, 1999
- International Business Machines Corporation
- David James Martens
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
High performance registers for pulsed logic
- Patent number 5,926,487
- Issue date Jul 20, 1999
- International Business Machines Corporation
- Terry Ivan Chappell
- G01 - MEASURING TESTING
Information Patent Grant
Latch structure for ripple domino logic
- Patent number 5,896,046
- Issue date Apr 20, 1999
- International Business Machines Corporation
- Andrew Augustus Bjorksten
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
System and method for testing self-timed memory arrays
- Patent number 5,896,399
- Issue date Apr 20, 1999
- International Business Machines Corporation
- George McNeil Lattimore
- G11 - INFORMATION STORAGE
Information Patent Grant
Creating inversions in ripple domino logic
- Patent number 5,892,372
- Issue date Apr 6, 1999
- International Business Machines Corporation
- Michael Kevin Ciraula
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method and apparatus for fast parallel determination of queue entries
- Patent number 5,822,752
- Issue date Oct 13, 1998
- International Business Machines Corporation
- Hoichi Cheong
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dynamic circuit having improved noise immunity and method therefor
- Patent number 5,818,264
- Issue date Oct 6, 1998
- International Business Machines Corporation
- Michael Kevin Ciraula
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Power-saving dynamic circuit
- Patent number 5,757,205
- Issue date May 26, 1998
- International Business Machines Corporation
- Michael Kevin Ciraula
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
CONFIGURATION OF MULTI-DIE MODULES WITH THROUGH-SILICON VIAS
- Publication number 20190332561
- Publication date Oct 31, 2019
- ADVANCED MICRO DEVICES, INC.
- Russell Schreiber
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FLEXIBILE INTERFACES USING THROUGH-SILICON VIA TECHNOLOGY
- Publication number 20190268086
- Publication date Aug 29, 2019
- ADVANCED MICRO DEVICES, INC.
- John Wuu
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
STAGED BITLINE PRECHARGE
- Publication number 20190189196
- Publication date Jun 20, 2019
- ADVANCED MICRO DEVICES, INC.
- Andrew ROBISON
- G11 - INFORMATION STORAGE
Information Patent Application
ERROR INJECTION FOR ASSESSMENT OF ERROR DETECTION AND CORRECTION TE...
- Publication number 20190188064
- Publication date Jun 20, 2019
- ADVANCED MICRO DEVICES, INC.
- Michael K. CIRAULA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SWIZZLING IN 3D STACKED MEMORY
- Publication number 20190129651
- Publication date May 2, 2019
- Advanced Micro Devices, Inc.
- John WUU
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PREDICTIVE MULTISTAGE COMPARISON FOR ASSOCIATIVE MEMORY
- Publication number 20180052770
- Publication date Feb 22, 2018
- Advanced Micro Devices, Inc.
- Carson Donahue Henrion
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY ELEMENTS FOR PERFORMING AN ALLOCATION OPERATION AND RELATED...
- Publication number 20120131279
- Publication date May 24, 2012
- Advanced Micro Devices, Inc.
- Michael CIRAULA
- G06 - COMPUTING CALCULATING COUNTING

Michael K. Ciraula

Person

Patents Grantslast 30 patents

Staged bitline precharge

Flexibile interfaces using through-silicon via technology

Configuration of multi-die modules with through-silicon vias

Error injection for assessment of error detection and correction te...

Swizzling in 3D stacked memory

Predictive multistage comparison for associative memory

Memory elements for performing an allocation operation and related...

Wafer stage storage structure speed testing

Multi-ported register cell with randomly accessible history

Memory array with global bitline domino read/write scheme

Decode structure with parallel rotation

Circular buffer using age vectors

Circular buffer using grouping for find first function

Elimination of SOI parasitic bipolar effect

Power-saving dynamic circuit

Circuit having anti-charge share characteristics and method therefore

Conditional restore for RAM based on feedback from a RAM cell to pr...

Initialization of floating body dynamic circuitry

Method and system for load data formatting and improved method for...

Conditional restore for SRAM

Memory array and method for writing data to memory

Conditional restore for execution unit

Translation shadow array adder-decoder circuit for selecting consec...

High performance registers for pulsed logic

Latch structure for ripple domino logic

System and method for testing self-timed memory arrays

Creating inversions in ripple domino logic

Method and apparatus for fast parallel determination of queue entries

Dynamic circuit having improved noise immunity and method therefor

Power-saving dynamic circuit

Patents Applicationslast 30 patents

CONFIGURATION OF MULTI-DIE MODULES WITH THROUGH-SILICON VIAS

FLEXIBILE INTERFACES USING THROUGH-SILICON VIA TECHNOLOGY

STAGED BITLINE PRECHARGE

ERROR INJECTION FOR ASSESSMENT OF ERROR DETECTION AND CORRECTION TE...

SWIZZLING IN 3D STACKED MEMORY

PREDICTIVE MULTISTAGE COMPARISON FOR ASSOCIATIVE MEMORY

MEMORY ELEMENTS FOR PERFORMING AN ALLOCATION OPERATION AND RELATED...