Michael K. Harper

Person

Hillsboro, OR, US

People

Patents Grantslast 30 patents

Information Patent Grant
Fabrication of gate-all-around integrated circuit structures having...
- Patent number 12,068,314
- Issue date Aug 20, 2024
- Intel Corporation
- Leonard P. Guler
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Plug and recess process for dual metal gate on stacked nanoribbon d...
- Patent number 12,046,652
- Issue date Jul 23, 2024
- Intel Corporation
- Nicole Thomas
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Fabrication of gate-all-around integrated circuit structures having...
- Patent number 11,990,472
- Issue date May 21, 2024
- Intel Corporation
- Leonard P. Guler
- G11 - INFORMATION STORAGE
Information Patent Grant
1D vertical edge blocking (VEB) via and plug
- Patent number 11,972,979
- Issue date Apr 30, 2024
- Intel Corporation
- Leonard P. Guler
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
1D vertical edge blocking (VEB) via and plug
- Patent number 11,721,580
- Issue date Aug 8, 2023
- Intel Corporation
- Leonard P. Guler
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Gate-all-around integrated circuit structures having fin stack isol...
- Patent number 11,594,637
- Issue date Feb 28, 2023
- Intel Corporation
- Leonard P. Guler
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Non-planar transistors with channel regions having varying widths
- Patent number 11,569,231
- Issue date Jan 31, 2023
- Intel Corporation
- Stephen D Snyder
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Sacrificial material for stripping masking layers
- Patent number 9,916,988
- Issue date Mar 13, 2018
- Intel Corporation
- Shakuntala Sundararajan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Trigate transistor structure with unrecessed field insulator and th...
- Patent number 9,905,693
- Issue date Feb 27, 2018
- Intel Corporation
- Michael L. Hattendorf
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Trigate transistor structure with unrecessed field insulator and th...
- Patent number 9,768,249
- Issue date Sep 19, 2017
- Intel Corporation
- Michael L. Hattendorf
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Substrate fins with different heights
- Patent number 8,629,039
- Issue date Jan 14, 2014
- Intel Corporation
- Willy Rachmady
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Substrate fins with different heights
- Patent number 8,441,074
- Issue date May 14, 2013
- Intel Corporation
- Willy Rachmady
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Recessed workfunction metal in CMOS transistor gates
- Patent number 8,377,771
- Issue date Feb 19, 2013
- Intel Corporation
- Willy Rachmady
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Feature size reduction
- Patent number 8,314,034
- Issue date Nov 20, 2012
- Intel Corporation
- Elliot N. Tan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Recessed workfunction metal in CMOS transistor gates
- Patent number 8,193,641
- Issue date Jun 5, 2012
- Intel Corporation
- Willy Rachmady
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Double patterning with single hard mask
- Patent number 7,977,248
- Issue date Jul 12, 2011
- Intel Corporation
- Elliot Tan
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
FABRICATION OF GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING...
- Publication number 20240363628
- Publication date Oct 31, 2024
- Intel Corporation
- Leonard P. GULER
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PLUG AND RECESS PROCESS FOR DUAL METAL GATE ON STACKED NANORIBBON D...
- Publication number 20240332389
- Publication date Oct 3, 2024
- Intel Corporation
- Nicole THOMAS
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FABRICATION OF GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING...
- Publication number 20240178226
- Publication date May 30, 2024
- Intel Corporation
- Leonard P. GULER
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
1D VERTICAL EDGE BLOCKING (VEB) VIA AND PLUG
- Publication number 20230326794
- Publication date Oct 12, 2023
- Intel Corporation
- Leonard P. GULER
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING FIN STACK ISOL...
- Publication number 20230163215
- Publication date May 25, 2023
- Intel Corporation
- Leonard P. GULER
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FABRICATION OF GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING...
- Publication number 20220093592
- Publication date Mar 24, 2022
- Intel Corporation
- Leonard P. GULER
- G11 - INFORMATION STORAGE
Information Patent Application
FABRICATION OF GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING...
- Publication number 20220093589
- Publication date Mar 24, 2022
- Intel Corporation
- Leonard P. GULER
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PLUG AND RECESS PROCESS FOR DUAL METAL GATE ON STACKED NANORIBBON D...
- Publication number 20210408257
- Publication date Dec 30, 2021
- Intel Corporation
- Nicole THOMAS
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING FIN STACK ISOL...
- Publication number 20210305430
- Publication date Sep 30, 2021
- Intel Corporation
- Leonard P. GULER
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING LOW ASPECT RAT...
- Publication number 20210202478
- Publication date Jul 1, 2021
- Intel Corporation
- Biswajeet GUHA
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
RECESSED GATE OXIDE ON THE SIDEWALL OF GATE TRENCH
- Publication number 20200403081
- Publication date Dec 24, 2020
- Seung Hoon Sung
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
1D VERTICAL EDGE BLOCKING (VEB) VIA AND PLUG
- Publication number 20200388534
- Publication date Dec 10, 2020
- Intel Corporation
- Leonard P. GULER
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
NON-PLANAR TRANSISTORS WITH CHANNEL REGIONS HAVING VARYING WIDTHS
- Publication number 20200295002
- Publication date Sep 17, 2020
- Intel Corporation
- Stephen D. Snyder
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TRIGATE TRANSISTOR STRUCTURE WITH UNRECESSED FIELD INSULATOR AND TH...
- Publication number 20170323965
- Publication date Nov 9, 2017
- Intel Corporation
- Michael L. HATTENDORF
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SACRIFICIAL MATERIAL FOR STRIPPING MASKING LAYERS
- Publication number 20160203999
- Publication date Jul 14, 2016
- SHAKUNTALA SUNDARARAJAN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TRIGATE TRANSISTOR STRUCTURE WITH UNRECESSED FIELD INSULATOR AND TH...
- Publication number 20160204193
- Publication date Jul 14, 2016
- Michael L. HATTENDORF
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SUBSTRATE FINS WITH DIFFERENT HEIGHTS
- Publication number 20130273710
- Publication date Oct 17, 2013
- Willy Rachmady
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
RECESSED WORKFUNCTION METAL IN CMOS TRANSISTOR GATES
- Publication number 20120264285
- Publication date Oct 18, 2012
- Intel Corporation
- Willy Rachmady
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FEATURE SIZE REDUCTION
- Publication number 20120164837
- Publication date Jun 28, 2012
- Elliot N. Tan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SUBSTRATE FINS WITH DIFFERENT HEIGHTS
- Publication number 20100276756
- Publication date Nov 4, 2010
- Willy Rachmady
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Substrate fins with different heights
- Publication number 20090321834
- Publication date Dec 31, 2009
- Willy Rachmady
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Double patterning with single hard mask
- Publication number 20090170316
- Publication date Jul 2, 2009
- Elliot Tan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Recessed workfunction metal in CMOS transistor gates
- Publication number 20070262451
- Publication date Nov 15, 2007
- Willy Rachmady
- H01 - BASIC ELECTRIC ELEMENTS

Michael K. Harper

Person

Patents Grantslast 30 patents

Fabrication of gate-all-around integrated circuit structures having...

Plug and recess process for dual metal gate on stacked nanoribbon d...

Fabrication of gate-all-around integrated circuit structures having...

1D vertical edge blocking (VEB) via and plug

1D vertical edge blocking (VEB) via and plug

Gate-all-around integrated circuit structures having fin stack isol...

Non-planar transistors with channel regions having varying widths

Sacrificial material for stripping masking layers

Trigate transistor structure with unrecessed field insulator and th...

Trigate transistor structure with unrecessed field insulator and th...

Substrate fins with different heights

Substrate fins with different heights

Recessed workfunction metal in CMOS transistor gates

Feature size reduction

Recessed workfunction metal in CMOS transistor gates

Double patterning with single hard mask

Patents Applicationslast 30 patents

FABRICATION OF GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING...

PLUG AND RECESS PROCESS FOR DUAL METAL GATE ON STACKED NANORIBBON D...

FABRICATION OF GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING...

1D VERTICAL EDGE BLOCKING (VEB) VIA AND PLUG

GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING FIN STACK ISOL...

FABRICATION OF GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING...

FABRICATION OF GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING...

PLUG AND RECESS PROCESS FOR DUAL METAL GATE ON STACKED NANORIBBON D...

GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING FIN STACK ISOL...

GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING LOW ASPECT RAT...

RECESSED GATE OXIDE ON THE SIDEWALL OF GATE TRENCH

1D VERTICAL EDGE BLOCKING (VEB) VIA AND PLUG

NON-PLANAR TRANSISTORS WITH CHANNEL REGIONS HAVING VARYING WIDTHS

TRIGATE TRANSISTOR STRUCTURE WITH UNRECESSED FIELD INSULATOR AND TH...

SACRIFICIAL MATERIAL FOR STRIPPING MASKING LAYERS

TRIGATE TRANSISTOR STRUCTURE WITH UNRECESSED FIELD INSULATOR AND TH...

SUBSTRATE FINS WITH DIFFERENT HEIGHTS

RECESSED WORKFUNCTION METAL IN CMOS TRANSISTOR GATES

FEATURE SIZE REDUCTION

SUBSTRATE FINS WITH DIFFERENT HEIGHTS

Substrate fins with different heights

Double patterning with single hard mask

Recessed workfunction metal in CMOS transistor gates