BACKGROUND
As semiconductor devices continue to be scaled to smaller sizes, lithography technology may not be able to pattern masking layers having the desired pitch. Accordingly, lithography may become a limiting factor in the scaling of semiconductor devices.
BRIEF DESCRIPTION OF THE DRAWINGS
The features and advantages of the various embodiments will become apparent from the following detailed description in which:
FIG. 1 illustrates an example substrate having a conductive layer, a hard mask layer formed on the conductive layer, and a first resist layer patterned on the hard mark layer, according to one embodiment;
FIG. 2 illustrates the example substrate after the hard mask is etched, according to one embodiment;
FIG. 3 illustrates the example substrate after the first resist layer is removed and a second resist layer is formed over the remaining hard mask, according to one embodiment;
FIG. 4 illustrates the example substrate after the second resist layer is patterned as a plurality of lines, according to one embodiment;
FIG. 5 illustrates the example substrate after the hard mask is etched using the second resist layer as the pattern, according to one embodiment;
FIG. 6 illustrates the example substrate after the lines are removed, according to one embodiment; and
FIG. 7 illustrates the example substrate after the active layer is etched using the hard mask fins as the pattern to create active fins, according to one embodiment.
DETAILED DESCRIPTION
In order to enable further scaling of semiconductor devices double patterning is used to pattern the active layers (e.g., polysilicon) to form devices (e.g., transistor fins, gate stacks) therein. The double patterning includes using multiple resist layers to pattern a single hard mask that is used to pattern the active layers. As the hard mask may remain on the active layers to act as a cap layer after etching the active layers, the thickness of the hard mask after patterning needs to be substantially conformal. In addition, the thickness of remaining hard mask should be substantially the desired thickness to act as the cap layer. The initial thickness of the hard mask may be twice the desired thickness of the cap layer. FIGS. 1-7 illustrate an example process to scale formation of the devices in the active layers using a double patterning of a single hard mask layer.
FIG. 1 illustrates an example semiconductor substrate having a conductive layer 100 (e.g., polysilicon), a hard mask layer 110 (e.g., dielectric) formed on the conductive layer 100, and a first resist layer patterned on the hard mark layer 110. The first resist layer (e.g., photo resist) is patterned as a plurality of lines 120 (first resist pattern), where the lines are separated by a pitch (e.g., 160 nm). The pitch may be the minimum pitch attainable with lithography and/or may be twice the desired pitch if lithography can not obtain the desired pitch. The hard mask layer 110 may have a thickness that is twice the desired thickness (e.g., thickness of the hard mask 110 utilized as a cap layer). The conductive layer 100, the hard mask layer 110, and the first resist layer may be formed through any number of known processes. The first resist pattern 120 may be created through any number of known processes including known lithography processes.
FIG. 2 illustrates the example substrate after the hard mask 110 is etched using the first resist pattern 120. The hard mask 110 is etched the desired thickness (half the thickness of the hard mask layer 110 is etched and half remains). The hard mask 110 that remains after etching is at the desired thickness. The hard mask 110 covered by the first resist pattern 120 is now a hard mask fin 112 that remains at twice the desired thickness. The hard mask layer 110 may be etched through any number of known processes.
FIG. 3 illustrates the example substrate after the first resist pattern 120 is removed and a second resist layer 130 (e.g., photo resist) is formed over the remaining hard mask 110, and hard mask fins 112. The second resist layer 130 may be formed through any number of known processes.
FIG. 4 illustrates the example substrate after the second resist layer 130 is patterned as a plurality of lines 132 (second resist pattern), where the lines 132 are separated by the pitch (e.g., twice the desired pitch) and the lines 132 are placed between the hard mask fins 112 previously formed by etching the hard mask 110 with the first resist pattern 120. The pitch between the lines 132 and the hard mask fins 112 is the desired pitch (e.g., 80 nm). The second resist layer 130 may be patterned through any number of known processes including known lithography processes.
FIG. 5 illustrates the example substrate after the hard mask 110 is etched using the second resist pattern 132. The hard mask 110 is etched the desired thickness. The hard mask 110 previously etched and not covered by the lines 132 is removed. The hard mask fins 112 are etched such that half the hard mask material is removed while half remains so that the hard mask fins 112 are the desired thickness. The hard mask 110 covered by the second resists pattern 132 is now a hard mask fin 116 that remains at the desired thickness. The fins 112, 116 are interwoven with each other and are the desired thickness. The hard mask layer 110 may be etched through any number of known processes.
FIG. 6 illustrates the example substrate after the second resist pattern 132 is removed. The fins 112, 116 are separated by the desired pitch. The second resist pattern 132 may be removed and through any number of known processes.
FIG. 7 illustrates the example substrate after the conductive layer 100 is etched using the hard mask fins 112, 116 as the pattern to create conductive fins 102. The conductive fins 102 may form gate electrodes, source regions, and/or drain regions. The hard mask fins 112, 116 may remain on the conductive fins 102 as the substrate is further processed.
While the embodiments described above have focused on using a hard mask layer that starts as twice the desired thickness in order to create the desired pitch using dual resist patterns and etchings, it is not limited thereto. Rather, the thickness could be increased and additional resist patterns and etchings could be used to further reduce the desired pitch without departing from the current scope. Furthermore, the embodiments were described with respect to creating fins at a desired pitch in active (e.g., polysilicon) layers but is not limited thereto.
Although the disclosure has been illustrated by reference to specific embodiments, it will be apparent that the disclosure is not limited thereto as various changes and modifications may be made thereto without departing from the scope. Reference to “one embodiment” or “an embodiment” means that a particular feature, structure or characteristic described therein is included in at least one embodiment. Thus, the appearances of the phrase “in one embodiment” or “in an embodiment” appearing in various places throughout the specification are not necessarily all referring to the same embodiment.
The various embodiments are intended to be protected broadly within the spirit and scope of the appended claims.
Patent Application
20090170316
