Michael LAOR

Person

Zichron Yaakov, IL

People

Patents Grantslast 30 patents

Information Patent Grant
Router and switch architecture
- Patent number 9,363,173
- Issue date Jun 7, 2016
- Compass Electro Optical Systems Ltd.
- Michael Laor
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Pipelined packet switching and queuing architecture
- Patent number 8,665,875
- Issue date Mar 4, 2014
- Oracle International Corporation
- Garry P. Epps
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Pipelined packet switching and queuing architecture
- Patent number 8,018,937
- Issue date Sep 13, 2011
- Cisco Technology, Inc.
- Garry P. Epps
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Pipelined packet switching and queuing architecture
- Patent number 7,643,486
- Issue date Jan 5, 2010
- Cisco Technology, Inc.
- David Belz
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
High-speed hardware implementation of RED congestion control algorithm
- Patent number 7,554,907
- Issue date Jun 30, 2009
- Cisco Technology, Inc.
- Garry P. Epps
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Methods and apparatus for processing packets including distributing...
- Patent number 7,304,999
- Issue date Dec 4, 2007
- Cisco Technology Inc.
- Vitaly Sukonik
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Synchronous pipelined switch using serial transmission
- Patent number 7,286,525
- Issue date Oct 23, 2007
- Cisco Technology, Inc.
- Michael Laor
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Pipelined packet switching and queuing architecture
- Patent number 6,980,552
- Issue date Dec 27, 2005
- Cisco Technology, Inc.
- David Belz
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Pipelined packet switching and queuing architecture
- Patent number 6,977,930
- Issue date Dec 20, 2005
- Cisco Technology, Inc.
- Garry P. Epps
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
High-speed hardware implementation of red congestion control algorithm
- Patent number 6,813,243
- Issue date Nov 2, 2004
- Cisco Technology, Inc.
- Garry P. Epps
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
High-speed hardware implementation of MDRR algorithm over a large n...
- Patent number 6,778,546
- Issue date Aug 17, 2004
- Cisco Technology, Inc.
- Garry P. Epps
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Flexible DMA engine for packet header modification
- Patent number 6,731,644
- Issue date May 4, 2004
- Cisco Technology, Inc.
- Garry P. Epps
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Flexible engine and data structure for packet header processing
- Patent number 6,721,316
- Issue date Apr 13, 2004
- Cisco Technology, Inc.
- Garry P. Epps
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Synchronous pipelined switch using serial transmission
- Patent number 6,424,649
- Issue date Jul 23, 2002
- Cisco Technology, Inc.
- Michael Laor
- H04 - ELECTRIC COMMUNICATION TECHNIQUE

Patents Applicationslast 30 patents

Information Patent Application
INTEGRATED FOLDED CLOS ARCHITECTURE
- Publication number 20170111294
- Publication date Apr 20, 2017
- Compass Electro Optical Systems Ltd.
- Michael LAOR
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Pipelined Packet Switching And Queuing Architecture
- Publication number 20120314707
- Publication date Dec 13, 2012
- Garry P. Epps
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
ROUTER AND SWITCH ARCHITECTURE
- Publication number 20120106562
- Publication date May 3, 2012
- Compass Electro Optical Systems Ltd.
- Michael Laor
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Pipelined packet switching and queuing architecture
- Publication number 20060050690
- Publication date Mar 9, 2006
- Garry P. Epps
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Pipelined packet switching and queuing architecture
- Publication number 20060039374
- Publication date Feb 23, 2006
- David Belz
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Hierarchical QoS behavioral model
- Publication number 20050249220
- Publication date Nov 10, 2005
- Cisco Technology, Inc.
- Robert Olsen
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Methods and apparatus for processing packets including distributing...
- Publication number 20040037322
- Publication date Feb 26, 2004
- Vitaly Sukonik
- H04 - ELECTRIC COMMUNICATION TECHNIQUE

Michael LAOR

Person

Patents Grantslast 30 patents

Router and switch architecture

Pipelined packet switching and queuing architecture

Pipelined packet switching and queuing architecture

Pipelined packet switching and queuing architecture

High-speed hardware implementation of RED congestion control algorithm

Methods and apparatus for processing packets including distributing...

Synchronous pipelined switch using serial transmission

Pipelined packet switching and queuing architecture

Pipelined packet switching and queuing architecture

High-speed hardware implementation of red congestion control algorithm

High-speed hardware implementation of MDRR algorithm over a large n...

Flexible DMA engine for packet header modification

Flexible engine and data structure for packet header processing

Synchronous pipelined switch using serial transmission

Patents Applicationslast 30 patents

INTEGRATED FOLDED CLOS ARCHITECTURE

Pipelined Packet Switching And Queuing Architecture

ROUTER AND SWITCH ARCHITECTURE

Pipelined packet switching and queuing architecture

Pipelined packet switching and queuing architecture

Hierarchical QoS behavioral model

Methods and apparatus for processing packets including distributing...