Michael R. Butts

Person

Beaverton, OR, US

People

Patents Grantslast 30 patents

Information Patent Grant
Non-sequentially configurable IC
- Patent number 8,810,277
- Issue date Aug 19, 2014
- Tbula, Inc.
- Herman Schmit
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Configurable circuits, IC's, and systems
- Patent number 8,638,119
- Issue date Jan 28, 2014
- Tabula, Inc.
- Herman Schmit
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Non-sequentially configurable IC
- Patent number 8,305,110
- Issue date Nov 6, 2012
- Tabula, Inc.
- Herman Schmit
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Configurable circuits, IC's, and systems
- Patent number 8,193,830
- Issue date Jun 5, 2012
- Tabula, Inc.
- Herman Schmit
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
System for reconfiguring a processor array
- Patent number 8,103,866
- Issue date Jan 24, 2012
- Nethra Imaging Inc.
- Michael R. Butts
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Non-sequentially configurable IC
- Patent number 7,948,266
- Issue date May 24, 2011
- Tabula, Inc.
- Herman Schmit
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method of mapping a user design defined for a user design cycle to...
- Patent number 7,872,496
- Issue date Jan 18, 2011
- Tabula, Inc.
- Herman Schmit
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
System of virtual data channels in an integrated circuit
- Patent number 7,801,033
- Issue date Sep 21, 2010
- Nethra Imaging, Inc.
- Anthony Mark Jones
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
System and method for performing design verification
- Patent number 7,792,933
- Issue date Sep 7, 2010
- Cadence Design Systems, Inc.
- Michael R. Butts
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Emulation system with time-multiplexed interconnect
- Patent number 7,739,097
- Issue date Jun 15, 2010
- Quickturn Design Systems Inc.
- Stephen P. Sample
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Non-sequentially configurable IC
- Patent number 7,667,486
- Issue date Feb 23, 2010
- Tabula, Inc.
- Herman Schmit
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Configurable circuits, IC's and systems
- Patent number 7,616,027
- Issue date Nov 10, 2009
- Tabula, Inc.
- Herman Schmit
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Configurable circuits, IC's, and systems
- Patent number 7,532,032
- Issue date May 12, 2009
- Tabula, Inc.
- Herman Schmit
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Configurable circuits, IC's, and systems
- Patent number 7,425,841
- Issue date Sep 16, 2008
- Tabula Inc.
- Herman Schmit
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Configurable circuits, IC's, and systems
- Patent number 7,408,382
- Issue date Aug 5, 2008
- Tabula, Inc.
- Herman Schmit
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Logic multiprocessor for FPGA implementation
- Patent number 7,260,794
- Issue date Aug 21, 2007
- Quickturn Design Systems, Inc.
- Michael R. Butts
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Configurable circuits, IC's, and systems
- Patent number 7,193,440
- Issue date Mar 20, 2007
- Herman Schmit
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Non-sequentially configurable IC
- Patent number 7,167,025
- Issue date Jan 23, 2007
- Herman Schmit
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Configurable circuits, IC's, and systems
- Patent number 7,157,933
- Issue date Jan 2, 2007
- Herman Schmit
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Configurable circuits, IC's, and systems
- Patent number 7,109,752
- Issue date Sep 19, 2006
- Herman Schmit
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
High-performance programmable logic architecture
- Patent number 6,882,176
- Issue date Apr 19, 2005
- Altera Corporation
- Kevin A. Norman
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method and apparatus for modeling using a hardware-software co-veri...
- Patent number 6,810,373
- Issue date Oct 26, 2004
- Synopsis, Inc.
- Bruce Harmon
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory circuit for use in hardware emulation system
- Patent number 6,732,068
- Issue date May 4, 2004
- Quickturn Design Systems Inc.
- Stephen P. Sample
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Optimized emulation and prototyping architecture
- Patent number 6,625,793
- Issue date Sep 23, 2003
- Quickturn Design Systems, Inc.
- Stephen P. Sample
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
High-performance programmable logic architecture
- Patent number 6,570,404
- Issue date May 27, 2003
- Altera Corporation
- Kevin A. Norman
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Programmable logic device having integrated probing structures
- Patent number 6,539,535
- Issue date Mar 25, 2003
- Quickturn Design Systems, Inc.
- Michael R. Butts
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Emulation system with time-multiplexed interconnect
- Patent number 6,377,912
- Issue date Apr 23, 2002
- Quickturn Design Systems, Inc.
- Stephen P. Sample
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
PLD with on-chip memory having a shadow register
- Patent number 6,353,552
- Issue date Mar 5, 2002
- Altera Corporation
- Stephen P. Sample
- G11 - INFORMATION STORAGE
Information Patent Grant
FPGA with on-chip multiport memory
- Patent number 6,317,367
- Issue date Nov 13, 2001
- Altera Corporation
- Stephen P. Sample
- G11 - INFORMATION STORAGE
Information Patent Grant
Optimized emulation and prototyping architecture
- Patent number 6,289,494
- Issue date Sep 11, 2001
- Quickturn Design Systems, Inc.
- Stephen P. Sample
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
Non-Sequentially Configurable IC
- Publication number 20150130508
- Publication date May 14, 2015
- Tabula, Inc.
- Herman Schmit
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
NON-SEQUENTIALLY CONFIGURABLE IC
- Publication number 20130099819
- Publication date Apr 25, 2013
- Herman Schmit
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CONFIGURABLE CIRCUITS, IC'S, AND SYSTEMS
- Publication number 20130021057
- Publication date Jan 24, 2013
- Herman Schmit
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
NON-SEQUENTIALLY CONFIGURABLE IC
- Publication number 20110267102
- Publication date Nov 3, 2011
- Herman Schmit
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Configurable Circuits, IC's, and Systems
- Publication number 20110133777
- Publication date Jun 9, 2011
- Herman Schmit
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Non-Sequentially Configurable IC
- Publication number 20100219859
- Publication date Sep 2, 2010
- Herman Schmit
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Non-Sequentially Configurable IC
- Publication number 20090167354
- Publication date Jul 2, 2009
- Herman Schmit
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Configurable Circuits, IC's and Systems
- Publication number 20090160481
- Publication date Jun 25, 2009
- Herman Schmit
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Configurable Circuits, IC's, and Systems
- Publication number 20090058461
- Publication date Mar 5, 2009
- Herman Schmit
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
SYSTEM FOR CONFIGURING A PROCESSOR ARRAY
- Publication number 20080235490
- Publication date Sep 25, 2008
- Anthony Mark Jones
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM FOR RECONFIGURING A PROCESSOR ARRAY
- Publication number 20080229093
- Publication date Sep 18, 2008
- Michael R. Butts
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Configurable Circuits, IC's and Systems
- Publication number 20070241777
- Publication date Oct 18, 2007
- Herman Schmit
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Configurable Circuits, IC's, and Systems
- Publication number 20070241787
- Publication date Oct 18, 2007
- Herman Schmit
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Non-Sequentially Configurable IC
- Publication number 20070241791
- Publication date Oct 18, 2007
- Herman Schmit
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Configurable circuits, IC's, and systems
- Publication number 20070241771
- Publication date Oct 18, 2007
- Herman Schmit
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
PROCESSOR HAVING MULTIPLE INSTRUCTION SOURCES AND EXECUTION MODES
- Publication number 20070169022
- Publication date Jul 19, 2007
- Anthony Mark Jones
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
RECONFIGURABLE PROCESSING ARRAY HAVING HIERARCHICAL COMMUNICATION N...
- Publication number 20070124565
- Publication date May 31, 2007
- Ambric, Inc.
- Anthony Mark Jones
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Configurable Circuits, IC's, and Systems
- Publication number 20070075737
- Publication date Apr 5, 2007
- Herman Schmit
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
System of virtual data channels in an integrated circuit
- Publication number 20070025382
- Publication date Feb 1, 2007
- Ambric, Inc.
- Anthony Mark Jones
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
System and method for performing design verification
- Publication number 20050022143
- Publication date Jan 27, 2005
- Cadence Design Systems, Inc.
- Michael R. Butts
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Logic multiprocessor for FPGA implementation
- Publication number 20040123258
- Publication date Jun 24, 2004
- Quickturn Design Systems, Inc.
- Michael R. Butts
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Emulation circuit with a hold time algorithm, logic analyzer and sh...
- Publication number 20030154458
- Publication date Aug 14, 2003
- Quickturn Design Systems, Inc.
- Michael R. Butts
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Emulation system with time-multiplexed interconnect
- Publication number 20030074178
- Publication date Apr 17, 2003
- Quickturn Design Systems, Inc.
- Stephen P. Sample
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Emulation circuit with a hold time algorithm, logic analyzer and sh...
- Publication number 20020162084
- Publication date Oct 31, 2002
- Michael R. Butts
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Memory circuit for use in hardware emulation system
- Publication number 20020161568
- Publication date Oct 31, 2002
- Quickturn Design Systems, Inc.
- Stephen P. Sample
- G01 - MEASURING TESTING
Information Patent Application
Optimized emulation and prototyping architecture
- Publication number 20020095649
- Publication date Jul 18, 2002
- Quickturn Design Systems, Inc.
- Stephen P. Sample
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PLD with on-chip memory having a shadow
- Publication number 20010017793
- Publication date Aug 30, 2001
- Stephen Sample
- G11 - INFORMATION STORAGE

Michael R. Butts

Person

Patents Grantslast 30 patents

Non-sequentially configurable IC

Configurable circuits, IC's, and systems

Non-sequentially configurable IC

Configurable circuits, IC's, and systems

System for reconfiguring a processor array

Non-sequentially configurable IC

Method of mapping a user design defined for a user design cycle to...

System of virtual data channels in an integrated circuit

System and method for performing design verification

Emulation system with time-multiplexed interconnect

Non-sequentially configurable IC

Configurable circuits, IC's and systems

Configurable circuits, IC's, and systems

Configurable circuits, IC's, and systems

Configurable circuits, IC's, and systems

Logic multiprocessor for FPGA implementation

Configurable circuits, IC's, and systems

Non-sequentially configurable IC

Configurable circuits, IC's, and systems

Configurable circuits, IC's, and systems

High-performance programmable logic architecture

Method and apparatus for modeling using a hardware-software co-veri...

Memory circuit for use in hardware emulation system

Optimized emulation and prototyping architecture

High-performance programmable logic architecture

Programmable logic device having integrated probing structures

Emulation system with time-multiplexed interconnect

PLD with on-chip memory having a shadow register

FPGA with on-chip multiport memory

Optimized emulation and prototyping architecture

Patents Applicationslast 30 patents

Non-Sequentially Configurable IC

NON-SEQUENTIALLY CONFIGURABLE IC

CONFIGURABLE CIRCUITS, IC'S, AND SYSTEMS

NON-SEQUENTIALLY CONFIGURABLE IC

Configurable Circuits, IC's, and Systems

Non-Sequentially Configurable IC

Non-Sequentially Configurable IC

Configurable Circuits, IC's and Systems

Configurable Circuits, IC's, and Systems

SYSTEM FOR CONFIGURING A PROCESSOR ARRAY

SYSTEM FOR RECONFIGURING A PROCESSOR ARRAY

Configurable Circuits, IC's and Systems

Configurable Circuits, IC's, and Systems

Non-Sequentially Configurable IC

Configurable circuits, IC's, and systems

PROCESSOR HAVING MULTIPLE INSTRUCTION SOURCES AND EXECUTION MODES

RECONFIGURABLE PROCESSING ARRAY HAVING HIERARCHICAL COMMUNICATION N...

Configurable Circuits, IC's, and Systems

System of virtual data channels in an integrated circuit

System and method for performing design verification

Logic multiprocessor for FPGA implementation

Emulation circuit with a hold time algorithm, logic analyzer and sh...

Emulation system with time-multiplexed interconnect

Emulation circuit with a hold time algorithm, logic analyzer and sh...

Memory circuit for use in hardware emulation system

Optimized emulation and prototyping architecture

PLD with on-chip memory having a shadow