Michael V. Ho

Person

Allen, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
Delay-locked loop clock sharing
- Patent number 11,217,298
- Issue date Jan 4, 2022
- Micron Technology, Inc.
- Younghoon Oh
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Semiconductor devices having electrostatic discharge layouts for re...
- Patent number 11,158,570
- Issue date Oct 26, 2021
- Micron Technology, Inc.
- Michael V. Ho
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Apparatuses and methods to perform duty cycle adjustment with back-...
- Patent number 11,145,354
- Issue date Oct 12, 2021
- Micron Technology, Inc.
- Michael V. Ho
- G11 - INFORMATION STORAGE
Information Patent Grant
Apparatuses and methods to perform duty cycle adjustment with back-...
- Patent number 10,950,291
- Issue date Mar 16, 2021
- Micron Technology, Inc.
- Michael V. Ho
- G11 - INFORMATION STORAGE
Information Patent Grant
Systems and methods for improving output signal quality in memory d...
- Patent number 10,825,506
- Issue date Nov 3, 2020
- Micron Technology, Inc.
- Michael V. Ho
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory with a reduced array data bus footprint
- Patent number 10,790,012
- Issue date Sep 29, 2020
- Micron Technology, Inc.
- Michael V. Ho
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor device with a time multiplexing mechanism for size ef...
- Patent number 10,747,693
- Issue date Aug 18, 2020
- Micron Technology, Inc.
- Michael V. Ho
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Semiconductor device with pseudo flow through scheme for power savings
- Patent number 10,747,470
- Issue date Aug 18, 2020
- Micron Technology, Inc.
- Michael V. Ho
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Mitigating line-to-line capacitive coupling in a memory die
- Patent number 10,699,774
- Issue date Jun 30, 2020
- Micron Technology, Inc.
- Michael V. Ho
- G11 - INFORMATION STORAGE
Information Patent Grant
Low power method and system for signal slew rate control
- Patent number 10,614,870
- Issue date Apr 7, 2020
- Micron Technology, Inc.
- Michael V. Ho
- G11 - INFORMATION STORAGE
Information Patent Grant
Systems and methods for generating stagger delays in memory devices
- Patent number 10,580,478
- Issue date Mar 3, 2020
- Micron Technology, Inc.
- Michael V. Ho
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and methods for generating stagger delays in memory devices
- Patent number 10,460,791
- Issue date Oct 29, 2019
- Micron Technology, Inc.
- Michael V. Ho
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and methods for conserving power in signal quality operatio...
- Patent number 10,438,649
- Issue date Oct 8, 2019
- Micron Technology, Inc.
- Michael V. Ho
- G11 - INFORMATION STORAGE
Information Patent Grant
Systems and methods for reducing coupling noise between propagation...
- Patent number 10,403,353
- Issue date Sep 3, 2019
- Micron Technology, Inc.
- Michael V. Ho
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory device with a latching mechanism
- Patent number 10,395,701
- Issue date Aug 27, 2019
- Micron Technology, Inc.
- Michael V. Ho
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory with a reduced array data bus footprint
- Patent number 10,366,743
- Issue date Jul 30, 2019
- Micron Technology, Inc.
- Michael V. Ho
- G11 - INFORMATION STORAGE
Information Patent Grant
Mitigating line-to-line capacitive coupling in a memory die
- Patent number 10,157,661
- Issue date Dec 18, 2018
- Micron Technology, Inc.
- Michael V. Ho
- G11 - INFORMATION STORAGE
Information Patent Grant
Input buffer protection
- Patent number 8,705,218
- Issue date Apr 22, 2014
- Micron Technology, Inc.
- Michael V. Ho
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Apparatus and method for external to internal clock generation
- Patent number 8,508,278
- Issue date Aug 13, 2013
- Micron Technology, Inc.
- Michael V. Ho
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Circuit and methods to protect input buffer
- Patent number 8,169,759
- Issue date May 1, 2012
- Micron Technology, Inc.
- Michael V. Ho
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Apparatus and method for external to internal clock generation
- Patent number 7,936,199
- Issue date May 3, 2011
- Micron Technology, Inc.
- Michael V. Ho
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Circuit for driving conductive line and testing conductive line for...
- Patent number 6,242,936
- Issue date Jun 5, 2001
- Texas Instruments Incorporated
- Michael Duc Ho
- G01 - MEASURING TESTING
Information Patent Grant
Low-power column decode circuit
- Patent number 6,088,293
- Issue date Jul 11, 2000
- Texas Instruments Incorporated
- Michael Duc Ho
- G11 - INFORMATION STORAGE
Information Patent Grant
Integrated circuit memory device having reduced stress across large...
- Patent number 5,867,421
- Issue date Feb 2, 1999
- Texas Instruments Incorporated
- Michael Ho
- G11 - INFORMATION STORAGE
Information Patent Grant
Write per bit with write mask information carried on the data path...
- Patent number 5,511,025
- Issue date Apr 23, 1996
- Texas Instruments Incorporated
- Scott E. Smith
- G11 - INFORMATION STORAGE
Information Patent Grant
Process of making and a DRAM standby charge pump with oscillator ha...
- Patent number 5,410,510
- Issue date Apr 25, 1995
- Texas Instruments Inc.
- Scott E. Smith
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
DELAY-LOCKED LOOP CLOCK SHARING
- Publication number 20210287731
- Publication date Sep 16, 2021
- Micron Technology, Inc.
- Younghoon Oh
- G11 - INFORMATION STORAGE
Information Patent Application
APPARATUSES AND METHODS TO PERFORM DUTY CYCLE ADJUSTMENT WITH BACK-...
- Publication number 20210201979
- Publication date Jul 1, 2021
- Micron Technology, Inc.
- Michael V. Ho
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
SYSTEMS AND METHODS FOR GENERATING STAGGER DELAYS IN MEMORY DEVICES
- Publication number 20200035290
- Publication date Jan 30, 2020
- Micron Technology, Inc.
- Michael V. Ho
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUSES AND METHODS FOR PIN CAPACITANCE REDUCTION INCLUDING BON...
- Publication number 20190363060
- Publication date Nov 28, 2019
- Micron Technology, Inc.
- Michael V. Ho
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR DEVICE WITH PSEUDO FLOW THROUGH SCHEME FOR POWER SAVINGS
- Publication number 20190347042
- Publication date Nov 14, 2019
- Micron Technology, Inc.
- Michael V. Ho
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SEMICONDUCTOR DEVICES HAVING ELECTROSTATIC DISCHARGE LAYOUTS FOR RE...
- Publication number 20190348363
- Publication date Nov 14, 2019
- Micron Technology, Inc.
- Michael V. Ho
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MEMORY DEVICES HAVING A REDUCED GLOBAL DATA PATH FOOTPRINT AND ASSO...
- Publication number 20190347219
- Publication date Nov 14, 2019
- Micron Technology, Inc.
- Michael V. Ho
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SEMICONDUCTOR DEVICE WITH A TIME MULTIPLEXING MECHANISM FOR SIZE EF...
- Publication number 20190347223
- Publication date Nov 14, 2019
- Micron Technology, Inc.
- Michael V. Ho
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY WITH A REDUCED ARRAY DATA BUS FOOTPRINT
- Publication number 20190348106
- Publication date Nov 14, 2019
- Micron Technology, Inc.
- Michael V. Ho
- G11 - INFORMATION STORAGE
Information Patent Application
LOW POWER METHOD AND SYSTEM FOR SIGNAL SLEW RATE CONTROL
- Publication number 20190348104
- Publication date Nov 14, 2019
- Micron Technology, Inc.
- Michael V. Ho
- G11 - INFORMATION STORAGE
Information Patent Application
SYSTEMS AND METHODS FOR CONSERVING POWER IN SIGNAL QUALITY OPERATIO...
- Publication number 20190259441
- Publication date Aug 22, 2019
- Micron Technology, Inc.
- Michael V. Ho
- G11 - INFORMATION STORAGE
Information Patent Application
SYSTEMS AND METHODS FOR GENERATING STAGGER DELAYS IN MEMORY DEVICES
- Publication number 20190259440
- Publication date Aug 22, 2019
- Micron Technology, Inc.
- Michael V. Ho
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEMS AND METHODS FOR IMPROVING OUTPUT SIGNAL QUALITY IN MEMORY D...
- Publication number 20190259445
- Publication date Aug 22, 2019
- Micron Technology, Inc.
- Michael V. Ho
- G11 - INFORMATION STORAGE
Information Patent Application
MITIGATING LINE-TO-LINE CAPACITIVE COUPLING IN A MEMORY DIE
- Publication number 20190108869
- Publication date Apr 11, 2019
- Micron Technology, Inc.
- Michael V. Ho
- G11 - INFORMATION STORAGE
Information Patent Application
INPUT BUFFER PROTECTION
- Publication number 20120215943
- Publication date Aug 23, 2012
- Michael V. Ho
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
APPARATUS AND METHOD FOR EXTERNAL TO INTERNAL CLOCK GENERATION
- Publication number 20110204949
- Publication date Aug 25, 2011
- Michael V. Ho
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUS AND METHOD FOR EXTERNAL TO INTERNAL CLOCK GENERATION
- Publication number 20090195287
- Publication date Aug 6, 2009
- Micron Technology, Inc.
- Michael V. Ho
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CIRCUIT AND METHODS TO PROTECT INPUT BUFFER
- Publication number 20090191836
- Publication date Jul 30, 2009
- Michael V. Ho
- H01 - BASIC ELECTRIC ELEMENTS

Michael V. Ho

Person

Patents Grantslast 30 patents

Delay-locked loop clock sharing

Semiconductor devices having electrostatic discharge layouts for re...

Apparatuses and methods to perform duty cycle adjustment with back-...

Apparatuses and methods to perform duty cycle adjustment with back-...

Systems and methods for improving output signal quality in memory d...

Memory with a reduced array data bus footprint

Semiconductor device with a time multiplexing mechanism for size ef...

Semiconductor device with pseudo flow through scheme for power savings

Mitigating line-to-line capacitive coupling in a memory die

Low power method and system for signal slew rate control

Systems and methods for generating stagger delays in memory devices

Systems and methods for generating stagger delays in memory devices

Systems and methods for conserving power in signal quality operatio...

Systems and methods for reducing coupling noise between propagation...

Memory device with a latching mechanism

Memory with a reduced array data bus footprint

Mitigating line-to-line capacitive coupling in a memory die

Input buffer protection

Apparatus and method for external to internal clock generation

Circuit and methods to protect input buffer

Apparatus and method for external to internal clock generation

Circuit for driving conductive line and testing conductive line for...

Low-power column decode circuit

Integrated circuit memory device having reduced stress across large...

Write per bit with write mask information carried on the data path...

Process of making and a DRAM standby charge pump with oscillator ha...

Patents Applicationslast 30 patents

DELAY-LOCKED LOOP CLOCK SHARING

APPARATUSES AND METHODS TO PERFORM DUTY CYCLE ADJUSTMENT WITH BACK-...

SYSTEMS AND METHODS FOR GENERATING STAGGER DELAYS IN MEMORY DEVICES

APPARATUSES AND METHODS FOR PIN CAPACITANCE REDUCTION INCLUDING BON...

SEMICONDUCTOR DEVICE WITH PSEUDO FLOW THROUGH SCHEME FOR POWER SAVINGS

SEMICONDUCTOR DEVICES HAVING ELECTROSTATIC DISCHARGE LAYOUTS FOR RE...

MEMORY DEVICES HAVING A REDUCED GLOBAL DATA PATH FOOTPRINT AND ASSO...

SEMICONDUCTOR DEVICE WITH A TIME MULTIPLEXING MECHANISM FOR SIZE EF...

MEMORY WITH A REDUCED ARRAY DATA BUS FOOTPRINT

LOW POWER METHOD AND SYSTEM FOR SIGNAL SLEW RATE CONTROL

SYSTEMS AND METHODS FOR CONSERVING POWER IN SIGNAL QUALITY OPERATIO...

SYSTEMS AND METHODS FOR GENERATING STAGGER DELAYS IN MEMORY DEVICES

SYSTEMS AND METHODS FOR IMPROVING OUTPUT SIGNAL QUALITY IN MEMORY D...

MITIGATING LINE-TO-LINE CAPACITIVE COUPLING IN A MEMORY DIE

INPUT BUFFER PROTECTION

APPARATUS AND METHOD FOR EXTERNAL TO INTERNAL CLOCK GENERATION

APPARATUS AND METHOD FOR EXTERNAL TO INTERNAL CLOCK GENERATION

CIRCUIT AND METHODS TO PROTECT INPUT BUFFER