Patent Application
20190347219
The present disclosure is related to memory systems, devices, and associated methods. In particular, the present disclosure is related to memory devices having a reduced global data path footprint.
Memory devices are widely used to store information related to various electronic devices such as computers, wireless communication devices, cameras, digital displays, and the like. Memory devices are frequently provided as internal, semiconductor, integrated circuits and/or external removable devices in computers or other electronic devices. There are many different types of memory, including volatile and non-volatile memory. Volatile memory, including random-access memory (RAM), static random access memory (SRAM), dynamic random access memory (DRAM), and synchronous dynamic random access memory (SDRAM), among others, may require a source of applied power to maintain its data. Non-volatile memory, by contrast, can retain its stored data even when not externally powered. Non-volatile memory is available in a wide variety of technologies, including flash memory (e.g., NAND and NOR), phase change memory (PCM), ferroelectric random access memory (FeRAM), resistive random access memory (RRAM), and magnetic random access memory (MRAM), among others.
Improving memory devices, generally, may include increasing memory cell density, increasing read/write speeds or otherwise reducing operational latency, increasing reliability, increasing data retention, reducing power consumption, or reducing manufacturing costs, among other metrics. One such other metric is reducing the size or footprint of the memory devices and/or components of the memory devices. Many manufacturers achieve size reduction through scaling. Manufacturers can also achieve size reduction through various architectural decisions and/or logic optimizations.
As discussed in greater detail below, the technology disclosed herein relates to memory systems and devices with a reduced global data path footprint. A person skilled in the art, however, will understand that the technology may have additional embodiments and that the technology may be practiced without several of the details of the embodiments described below with reference to the figures indicated below. In the illustrated embodiments below, the memory devices and systems are primarily described in the context of devices incorporating DRAM storage media. Memory devices configured in accordance with other embodiments of the present technology, however, can include other types of memory devices and systems incorporating other types of storage media, including PCM, SRAM, FRAM, RRAM, MRAM, read only memory (ROM), erasable programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), ferroelectric, magnetoresistive, and other storage media, including non-volatile, flash (e.g., NAND and/or NOR) storage media.
Several memory devices (e.g., DRAM memory devices) use groups of DC and/or power supply lines to shield dynamic signals sent through data lines in the memory devices. In memory devices with wide input/output (I/O) data and high speed operations, these shields are important to preserve and protect signal integrity. Many of these memory devices include multiple I/O circuit configurations to cater to different market segments. Often only one configuration is used, however, meaning that these memory devices carry the remaining configurations as overhead and wasted space. As described in greater detail below, memory devices configured in accordance with embodiments of the present technology use the overhead configurations to replace the shield lines, thereby reducing the size or footprint of global I/O data paths in the memory devices. In addition, these and other memory devices configured in accordance with embodiments of the present technology utilize a staggered firing scheme to separate the transition of signals on the global data lines to reduce coupling within the global data lines that is often caused by simultaneous switching.
As shown in
The memory device 100 may employ a plurality of external terminals that include command and address terminals coupled to a command bus and an address bus to receive command signals CMD and address signals ADDR, respectively. The memory device may further include a chip select terminal to receive a chip select signal CS, clock terminals to receive clock signals CK, CKF, WCK, and WCKF, data terminals DQ, DQS, DBI, and DMI, and power supply terminals VDD, VSS, VDDQ, and/or VSSQ.
As shown in the illustrated embodiment, the clock terminals may be supplied with external clock signals and complementary external clock signals. The external clock signals CK, CKF, WCK, and WCKF can be supplied to a clock input circuit 120. The CK and CKF signals and the WCK and WCKF signals can be complementary. Complementary clock signals can have opposite clock levels and can transition between the opposite clock levels at the same time. For example, when a clock signal is at a low clock level a complementary clock signal is at a high level, and when the clock signal is at a high clock level the complementary clock signal is at a low clock level. Moreover, when the clock signal transitions from the low clock level to the high clock level, the complementary clock signal transitions from the high clock level to the low clock level; and when the clock signal transitions from the high clock level to the low clock level, the complementary clock signal transitions from the low clock level to the high clock level.
Input buffers included in the clock input circuit 120 can receive the external clock signals. For example, when enabled by a CKE signal from command decoder 115, an input buffer can receive the CK and CKF signals. The clock input circuit 120 can receive the external clock signals to generate internal clock signals ICLK. The internal clock signals ICLK can be supplied to an internal clock circuit 130. The internal clock circuit 130 can provide various phase and frequency controlled internal clock signals based on the received internal clock signals ICLK and a clock enable signal CKE from command/address input circuit 105. For example, the internal clock circuit 130 can include a clock path (not shown in
The command terminals and address terminals may be supplied with an address signal and a bank address signal from outside. The address signal and the bank address signal supplied to the address terminals can be transferred, via the command/address input circuit 105, to an address decoder 110. The address decoder 110 can receive the address signals and supply a decoded row address signal (XADD) to the row decoder 140, and a decoded column address signal (YADD) to the column decoder 145. The address decoder 110 can also receive the bank address signal (BADD) and supply the bank address signal to both the row decoder 140 and the column decoder 145.
The command and address terminals may be supplied with command signals CMD, address signals ADDR, and chip selection signals CS, from a memory controller. The command signals may represent various memory commands from the memory controller (e.g., including access commands, which can include read commands and write commands). The select signal CS may be used to select the memory device 100 to respond to commands and addresses provided to the command and address terminals. When an active CS signal is provided to the memory device 100, the commands and addresses can be decoded and memory operations can be performed. The command signals CMD may be provided as internal command signals ICMD to the command decoder 115 via the command/address input circuit 105. The command decoder 115 may include circuits to decode the internal command signals ICMD to generate various internal signals and commands for performing memory operations, for example, a row command signal to select a word line and a column command signal to select a bit line. The internal command signals can also include output and input activation commands, such as clocked command. The command decoder 115 may further include one or more registers 118 for tracking various counts or values.
The power supply terminals may be supplied with power supply potentials VDD and VSS. These power supply potentials VDD and VSS can be supplied to an internal voltage generator circuit 170. The internal voltage generator circuit 170 can generate various internal potentials VPP, VOD, VARY, VPERI, and the like based on the power supply potentials VDD and VSS. The internal potential VPP can be used in row decoder 140, the internal potentials VOD and VARY can be used in sense amplifiers included in memory array 150, and the internal potential VPERI can be used in many other circuit blocks.
The power supply terminal may also be supplied with power supply potential VDDQ and/or VSSQ. The power supply potential VDDQ can be supplied to I/O circuit 160 together with the power supply potential VSS. The power supply potential VDDQ can be the same potential as the power supply potential VDD in an embodiment of the present technology. The power supply potential VDDQ can be a different potential from the power supply potential VDD in another embodiment of the present technology. However, the dedicated power supply potential VDDQ can be used for the input/output circuit 160 so that power supply noise generated by the input/output circuit 160 does not propagate to the other circuit blocks.
The read data may be provided at a time defined by read latency information that can be programmed in the memory device 100, for example, in a mode register (not shown in
When a write command is issued and a row address and a column address are timely supplied with the command, write data can be supplied to the data terminals DQ(0:7), DQ(8:15), LDQS, UDQS, LDQM, UDQM, DBI, and/or DMI according to the I/OCK clock signal. The write command may be received by the command decoder 115 (
The write data may be written in the memory cell designated by the row address and the column address. The write data may be provided to the data terminals at a time that is defined by write latency information. The write latency information can be programmed in the memory device 100, for example, in the mode register (not shown in
As discussed above, the global data lines are bi-directional signal paths that carry read and/or write data from and/or to the memory array 150 (
Depending on the configuration of the memory device 100, all or a subset of the global data lines and/or the data mask lines on the internal data bus 264 are used. For example, in an ×16 configuration of the memory device 100, all of the data terminals DQ(0:7) and DQ(8:15), the 128 corresponding global data lines, both data mask terminals LDQM and UDQM, and the 16 corresponding data mask lines are used. In ×4 and/or ×8 configurations of the memory device 100, on the other hand, only the lower data terminals DQ(0:7), the 64 corresponding global data lines, the lower data mask terminal LDQM, and/or the eight corresponding data mask lines are used. In these configurations, the data mask lines corresponding to the upper data mask terminal UDQM can be tied to a first state (e.g., a high state) to mask activity on the portion of the internal data bus 264 corresponding to the upper data terminals DQ(8:15). A single memory device can be configured to support each of the ×16, ×8 and ×4 configurations.
As shown in the illustrated embodiment, the device 400 can further include a fifth plurality of global data lines 450. In some embodiments, the fifth plurality of global data lines 450 can be used to incorporate other data, such as test mode data (e.g., compressed test mode data) and/or MPR data (e.g., MPR read data), onto the plurality of global data lines, and route them to the lower and upper terminals. The test mode data and/or MPR data on the fifth plurality of global data lines 450 can be separately controlled (e.g., by shared control logic with the other global data lines) and routed at appropriate times to their corresponding destinations. In some embodiments, the test mode data and/or MPR data on the fifth plurality of global data lines 450 can be transferred to their corresponding target destinations via shared global data lines along with other read and write data. The ability to share the global data lines amongst the MPR data, test mode data, and read and write data decreases the number of data lines needed for the device 400, thereby limiting the amount of space on the device 400 occupied by data lines. Furthermore, because the test mode data and/or MPR data is often not time sensitive, or at least not as time sensitive as the read and write data, the data of the fifth plurality of global data lines 450 can be controlled to be routed to the third and fourth pluralities of global data lines 430, 440, for example, only after the read and write data has been sent. Compared the device 300 described above, the fifth plurality of global data lines 450 can improve timing and routing conditions by ensuring that read and write data is prioritized over test mode and/or MPR data.
As further shown in the illustrated embodiment, the device 400 can include one or more multiplexers 475 positioned between (a) the first, second and fifth pluralities of global data lines 410, 420, 450 and (b) the third and fourth pluralities of global data lines 430, 440. The multiplexers 475 can multiplex (e.g., time multiplex) data from the first, second, and/or fifth pluralities of global data lines 410, 420, 450 onto the third and/or fourth pluralities of global data lines 430, 440 (i.e., from the memory array to the lower and/or upper terminals). As shown in the illustrated embodiment, the multiplexers 475 can also multiplex data being transferred in the opposite direction. That is, the multiplexers 475 can multiplex data coming from the third and/or fourth pluralities of global data lines 430, 440 onto the first, second and/or fifth pluralities of global data lines 410, 420, 450 (i.e., from the lower and/or upper terminals to the memory array). In some embodiments, individual signals having data can be grouped together in a phase or group of signals, and the group can be multiplexed onto individual lines of the third and fourth pluralities of global data lines 430, 440, or onto individual lines of the first, second and/or fifth pluralities of global data lines 410, 420, 450, in route to their target destinations. The individual signals can then be demultiplexed upon reaching their target destinations. By multiplexing multiple signals at once onto individual lines of the first, second, third, fourth and/or fifth pluralities of global data lines 410, 420, 430, 440, 450, the number of global data lines of the device 400 can be significantly reduced compared to, for example, the number of global data lines needed to operate device 300. As shown in the illustrated embodiment, the device 400 can also include one or more repeaters 470 and drivers 465. Each of the repeaters 470 and drivers 465 are configured to support monodirectional and bidirectional data transmission. As such, the number of repeaters 470 and drivers 465 needed for the device 400 can be significantly reduced compared to the numbers of repeaters and drivers needed for device 300.
As noted above, the device 400 includes a single-center architecture having a “Center” region. To control the transfer of data amongst the first and second pluralities of global data lines 410, 420 and the third and fourth pluralities of global data lines 430, 440, the device 400 utilizes a common control logic (not shown) located at or near the “Center” region. The control logic can utilize timing controls, as well as speed and power design criteria of the device 400, to optimize data transfer throughout the device 400. For example, the control logic can prioritize certain data streams (e.g., data having read and write functionality) over other data streams (e.g., test mode data and/or MPR data) that have less time criticality. In some embodiments, the control logic can further include combining individual signals into a group of signals that is multiplexed onto one of the global data lines and then demultiplexed at target destinations of the individual signals.
Embodiments of the present technology have multiple advantages over other devices previously used for data transfer on memory devices. For example, compared to the device 300 described above, the device 400 reduces the number of global data lines by allowing each of the global data lines to operate bidirectionally and transfer both read and write data on the same line. By reducing the number of global data lines on the device 400, and therein reducing the global data path for a particular data stream, the device 400 can be made smaller. Additionally, by orienting the first and second pluralities of global data lines 410, 420 in a center region of the device 400, control logic can be shared between the first and second pluralities of global data lines 410, 420, as well as between the third and fourth pluralities of global data lines 430, 440. This shared control logic allows for more efficient data routing, which can result in faster routing and less power output.
The above detailed descriptions of embodiments of the technology are not intended to be exhaustive or to limit the technology to the precise form disclosed above. Although specific embodiments of, and examples for, the technology are described above for illustrative purposes, various equivalent modifications are possible within the scope of the technology as those of ordinary skill in the relevant art will recognize. For example, although steps are presented in a given order, alternative embodiments may perform steps in a different order. The various embodiments described herein may also be combined to provide further embodiments.
From the foregoing, it will be appreciated that specific embodiments of the technology have been described herein for purposes of illustration, but well-known structures and functions have not been shown or described in detail to avoid unnecessarily obscuring the description of the embodiments of the technology. Where the context permits, singular or plural terms may also include the plural or singular term, respectively. Moreover, unless the word “or” is expressly limited to mean only a single item exclusive from the other items in reference to a list of two or more items, then the use of “or” in such a list is to be interpreted as including (a) any single item in the list, (b) all of the items in the list, or (c) any combination of the items in the list. Additionally, the terms “comprising,” “including,” “having,” and “with” are used throughout to mean including at least the recited feature(s) such that any greater number of the same feature and/or additional types of other features are not precluded.
From the foregoing, it will also be appreciated that various modifications may be made without deviating from the disclosure. For example, one of ordinary skill in the art will understand that various components of the technology can be further divided into subcomponents, or that various components and functions of the technology may be combined and integrated. In addition, certain aspects of the technology described in the context of particular embodiments may also be combined or eliminated in other embodiments. Furthermore, although advantages associated with certain embodiments of the new technology have been described in the context of those embodiments, other embodiments may also exhibit such advantages and not all embodiments need necessarily exhibit such advantages to fall within the scope of the technology. Accordingly, the disclosure and associated technology can encompass other embodiments not expressly shown or described.
