Michael W. Leddige

Person

Beaverton, OR, US

People

Patents Grantslast 30 patents

Information Patent Grant
Mode selective balanced encoded interconnect
- Patent number 10,078,612
- Issue date Sep 18, 2018
- Intel Corporation
- Michael W. Leddige
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Crosstalk aware decoding for a data bus
- Patent number 9,632,961
- Issue date Apr 25, 2017
- Intel Corporation
- Olufemi B. Oluwafemi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
High bandwidth connector for internal and external IO interfaces
- Patent number 9,391,378
- Issue date Jul 12, 2016
- Intel Corporation
- Michael Leddige
- Y10 - TECHNICAL SUBJECTS COVERED BY FORMER USPC
Information Patent Grant
Crosstalk aware encoding for a data bus
- Patent number 9,330,039
- Issue date May 3, 2016
- Intel Corporation
- Stephen H. Hall
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Interchangeable connection arrays for double-sided DIMM placement
- Patent number 8,775,991
- Issue date Jul 8, 2014
- Intel Corporation
- Michael W. Leddige
- G11 - INFORMATION STORAGE
Information Patent Grant
Dynamic configuration of potential links between processing elements
- Patent number 8,649,262
- Issue date Feb 11, 2014
- Intel Corporation
- Sadagopan Srinivasan
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Providing address range coherency capability to a device
- Patent number 8,631,208
- Issue date Jan 14, 2014
- Intel Corporation
- Zhen Fang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Interchangeable connection arrays for double-sided DIMM placement
- Patent number 8,438,515
- Issue date May 7, 2013
- Intel Corporation
- Michael W. Leddige
- G11 - INFORMATION STORAGE
Information Patent Grant
Interchangeable connection arrays for double-sided DIMM placement
- Patent number 8,099,687
- Issue date Jan 17, 2012
- Intel Corporation
- Michael W. Leddige
- G11 - INFORMATION STORAGE
Information Patent Grant
Stacking integrated circuit dies
- Patent number 7,772,708
- Issue date Aug 10, 2010
- Intel Corporation
- Michael Leddige
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Systems and arrangements for interconnecting integrated circuit dies
- Patent number 7,514,773
- Issue date Apr 7, 2009
- Intel Corporation
- Michael Leddige
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Technique for blind-mating daughtercard to mainboard
- Patent number 7,402,048
- Issue date Jul 22, 2008
- Intel Corporation
- Pascal C. Meier
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Memory system and method to reduce reflection and signal degradation
- Patent number 7,194,572
- Issue date Mar 20, 2007
- Intel Corporation
- Michael W. Leddige
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Circulator chain memory command and address bus topology
- Patent number 7,133,962
- Issue date Nov 7, 2006
- Intel Corporation
- Michael W. Leddige
- G11 - INFORMATION STORAGE
Information Patent Grant
Systems with modules sharing terminations
- Patent number 6,918,078
- Issue date Jul 12, 2005
- Intel Corporation
- James A. McCall
- G11 - INFORMATION STORAGE
Information Patent Grant
System and method for bit encoding to increase data transfer rate
- Patent number 6,891,899
- Issue date May 10, 2005
- Intel Corporation
- Stephen H. Hall
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Low weight data encoding for minimal power delivery impact
- Patent number 6,788,222
- Issue date Sep 7, 2004
- Intel Corporation
- Stephen H. Hall
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Systems having modules with selectable on die terminations
- Patent number 6,724,082
- Issue date Apr 20, 2004
- Intel Corporation
- James A. McCall
- G11 - INFORMATION STORAGE
Information Patent Grant
Split delay transmission line
- Patent number 6,711,640
- Issue date Mar 23, 2004
- Intel Corporation
- Michael W. Leddige
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Computer assembly with stub traces coupled to vias to add capacitan...
- Patent number 6,708,243
- Issue date Mar 16, 2004
- Intel Corporation
- Michael W. Leddige
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Memory module using DRAM package to match channel impedance
- Patent number 6,686,762
- Issue date Feb 3, 2004
- Intel Corporation
- Michael W. Leddige
- G11 - INFORMATION STORAGE
Information Patent Grant
Systems with modules and clocking therefore
- Patent number 6,631,083
- Issue date Oct 7, 2003
- Intel Corporation
- James A. McCall
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for implementing multiple memory buses on a me...
- Patent number 6,587,912
- Issue date Jul 1, 2003
- Intel Corporation
- Michael W. Leddige
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Capacitively loaded continuity module
- Patent number 6,539,449
- Issue date Mar 25, 2003
- Intel Corporation
- Michael W. Leddige
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Memory module with parallel stub traces
- Patent number 6,515,555
- Issue date Feb 4, 2003
- Intel Corporation
- Michael W. Leddige
- G11 - INFORMATION STORAGE
Information Patent Grant
Method for implementing multiple memory buses on a memory module
- Patent number 6,477,614
- Issue date Nov 5, 2002
- Intel Corporation
- Michael W. Leddige
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-layer printed circuit board with signal traces of varying width
- Patent number 6,366,466
- Issue date Apr 2, 2002
- Intel Corporation
- Michael W. Leddige
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Multilayer printed circuit board with placebo vias for controlling...
- Patent number 6,362,973
- Issue date Mar 26, 2002
- Intel Corporation
- Michael W. Leddige
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Method and apparatus for matched length routing of back-to-back pac...
- Patent number 6,353,539
- Issue date Mar 5, 2002
- Intel Corporation
- Bryce D. Horine
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Method and apparatus for implementing a serial memory architecture
- Patent number 6,144,576
- Issue date Nov 7, 2000
- Intel Corporation
- Michael W. Leddige
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
RESILIENT ELECTRICAL CONNECTORS FOR ELECTROMAGNETIC INTERFERENCE SH...
- Publication number 20220139843
- Publication date May 5, 2022
- Intel Corporation
- Jun LU
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
IMPEDANCE MATCHING IN A TRANSMISSION LINE
- Publication number 20160173055
- Publication date Jun 16, 2016
- Intel Corporation
- Michael W. Leddige
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MODE SELECTIVE BALANCED ENCODED INTERCONNECT
- Publication number 20160026597
- Publication date Jan 28, 2016
- Intel Corporation
- Michael W. Leddige
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD, APPARATUS AND SYSTEM FOR SINGLE-ENDED COMMUNICATION OF TRAN...
- Publication number 20150269109
- Publication date Sep 24, 2015
- Bryan L. Spry
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HIGH BANDWIDTH CONNECTOR FOR INTERNAL AND EXTERNAL IO INTERFACES
- Publication number 20140377968
- Publication date Dec 25, 2014
- Michael Leddige
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CROSSTALK AWARE DECODING FOR A DATA BUS
- Publication number 20140181348
- Publication date Jun 26, 2014
- Olufemi B. Oluwafemi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CROSSTALK AWARE DECODING FOR A DATA BUS
- Publication number 20140181358
- Publication date Jun 26, 2014
- Chaitanya Sreerama
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CROSSTALK AWARE ENCODING FOR A DATA BUS
- Publication number 20140181357
- Publication date Jun 26, 2014
- Stephen H. Hall
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTERCHANGEABLE CONNECTION ARRAYS FOR DOUBLE-SIDED DIMM PLACEMENT
- Publication number 20130341790
- Publication date Dec 26, 2013
- Michael W. Leddige
- G11 - INFORMATION STORAGE
Information Patent Application
INTERCHANGEABLE CONNECTION ARRAYS FOR DOUBLE-SIDED DIMM PLACEMENT
- Publication number 20120199973
- Publication date Aug 9, 2012
- Michael W. Leddige
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Application
Providing Address Range Coherency Capability To A Device
- Publication number 20100191920
- Publication date Jul 29, 2010
- Zhen Fang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DYNAMIC CONFIGURATION OF POTENTIAL LINKS BETWEEN PROCESSING ELEMENTS
- Publication number 20100080132
- Publication date Apr 1, 2010
- Sadagopan Srinivasan
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Memory module routing
- Publication number 20080266778
- Publication date Oct 30, 2008
- INTEL CORPORATION
- John T. Sprietsma
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Application
Interchangeable connection arrays for double-sided DIMM placement
- Publication number 20080062734
- Publication date Mar 13, 2008
- Michael W. Leddige
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Application
Systems and arrangements for interconnecting integrated circuit dies
- Publication number 20080054493
- Publication date Mar 6, 2008
- Michael Leddige
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Systems and arrangements for interconnecting integrated circuit dies
- Publication number 20080054488
- Publication date Mar 6, 2008
- Michael Leddige
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Technique for blind-mating daughtercard to mainboard
- Publication number 20070238322
- Publication date Oct 11, 2007
- Pascal C. Meier
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Memory module circuit board layer routing
- Publication number 20060137903
- Publication date Jun 29, 2006
- John T. Sprietsma
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Memory module routing
- Publication number 20060139983
- Publication date Jun 29, 2006
- John T. Sprietsma
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Application
Interchangeable connection arrays for double-sided memory module pl...
- Publication number 20050195629
- Publication date Sep 8, 2005
- Michael W. Leddige
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Application
Circulator chain memory command and address bus topology
- Publication number 20050055499
- Publication date Mar 10, 2005
- Michael W. Leddige
- G11 - INFORMATION STORAGE
Information Patent Application
Split T-chain memory command and address bus topology
- Publication number 20050033905
- Publication date Feb 10, 2005
- Michael W. Leddige
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and assembly having a matched filter connector
- Publication number 20040225807
- Publication date Nov 11, 2004
- Michael W. Leddige
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Multi-level coding for digital communication
- Publication number 20030063677
- Publication date Apr 3, 2003
- Intel Corporation
- Jason A. Mix
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Apparatus and method for a selectable Ron driver impedance
- Publication number 20030056128
- Publication date Mar 20, 2003
- Michael W. Leddige
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Systems having modules with selectable on die terminations
- Publication number 20030016512
- Publication date Jan 23, 2003
- James A. McCall
- G11 - INFORMATION STORAGE
Information Patent Application
Systems with modules sharing terminations
- Publication number 20030018940
- Publication date Jan 23, 2003
- James A. McCall
- G11 - INFORMATION STORAGE
Information Patent Application
Systems with modules and clocking therefore
- Publication number 20030016549
- Publication date Jan 23, 2003
- James A. McCall
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Low weight data encoding for minimal power delivery impact
- Publication number 20020138805
- Publication date Sep 26, 2002
- Stephen H. Hall
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
System and method for bit encoding to increase data transfer rate
- Publication number 20020131518
- Publication date Sep 19, 2002
- Stephen H. Hall
- H04 - ELECTRIC COMMUNICATION TECHNIQUE

Michael W. Leddige

Person

Patents Grantslast 30 patents

Mode selective balanced encoded interconnect

Crosstalk aware decoding for a data bus

High bandwidth connector for internal and external IO interfaces

Crosstalk aware encoding for a data bus

Interchangeable connection arrays for double-sided DIMM placement

Dynamic configuration of potential links between processing elements

Providing address range coherency capability to a device

Interchangeable connection arrays for double-sided DIMM placement

Interchangeable connection arrays for double-sided DIMM placement

Stacking integrated circuit dies

Systems and arrangements for interconnecting integrated circuit dies

Technique for blind-mating daughtercard to mainboard

Memory system and method to reduce reflection and signal degradation

Circulator chain memory command and address bus topology

Systems with modules sharing terminations

System and method for bit encoding to increase data transfer rate

Low weight data encoding for minimal power delivery impact

Systems having modules with selectable on die terminations

Split delay transmission line

Computer assembly with stub traces coupled to vias to add capacitan...

Memory module using DRAM package to match channel impedance

Systems with modules and clocking therefore

Method and apparatus for implementing multiple memory buses on a me...

Capacitively loaded continuity module

Memory module with parallel stub traces

Method for implementing multiple memory buses on a memory module

Multi-layer printed circuit board with signal traces of varying width

Multilayer printed circuit board with placebo vias for controlling...

Method and apparatus for matched length routing of back-to-back pac...

Method and apparatus for implementing a serial memory architecture

Patents Applicationslast 30 patents

RESILIENT ELECTRICAL CONNECTORS FOR ELECTROMAGNETIC INTERFERENCE SH...

IMPEDANCE MATCHING IN A TRANSMISSION LINE

MODE SELECTIVE BALANCED ENCODED INTERCONNECT

METHOD, APPARATUS AND SYSTEM FOR SINGLE-ENDED COMMUNICATION OF TRAN...

HIGH BANDWIDTH CONNECTOR FOR INTERNAL AND EXTERNAL IO INTERFACES

CROSSTALK AWARE DECODING FOR A DATA BUS

CROSSTALK AWARE DECODING FOR A DATA BUS

CROSSTALK AWARE ENCODING FOR A DATA BUS

INTERCHANGEABLE CONNECTION ARRAYS FOR DOUBLE-SIDED DIMM PLACEMENT

INTERCHANGEABLE CONNECTION ARRAYS FOR DOUBLE-SIDED DIMM PLACEMENT

Providing Address Range Coherency Capability To A Device

DYNAMIC CONFIGURATION OF POTENTIAL LINKS BETWEEN PROCESSING ELEMENTS

Memory module routing

Interchangeable connection arrays for double-sided DIMM placement

Systems and arrangements for interconnecting integrated circuit dies

Systems and arrangements for interconnecting integrated circuit dies

Technique for blind-mating daughtercard to mainboard

Memory module circuit board layer routing

Memory module routing

Interchangeable connection arrays for double-sided memory module pl...

Circulator chain memory command and address bus topology

Split T-chain memory command and address bus topology

Method and assembly having a matched filter connector

Multi-level coding for digital communication

Apparatus and method for a selectable Ron driver impedance

Systems having modules with selectable on die terminations

Systems with modules sharing terminations

Systems with modules and clocking therefore

Low weight data encoding for minimal power delivery impact

System and method for bit encoding to increase data transfer rate