Michio Komoda

Person

Hyogo, JP

People

Patents Grantslast 30 patents

Information Patent Grant
Delay calculation method capable of calculating delay time with sma...
- Patent number 7,496,491
- Issue date Feb 24, 2009
- Renesas Technology Corp.
- Michio Komoda
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Clock forming method for semiconductor integrated circuit and progr...
- Patent number 7,479,825
- Issue date Jan 20, 2009
- Renesas Technology Corp.
- Michio Komoda
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Delay time estimation method and recording medium storing estimatio...
- Patent number 7,127,385
- Issue date Oct 24, 2006
- Renesas Technology Corp.
- Michio Komoda
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method of formulating load model for glitch analysis and recording...
- Patent number 7,039,573
- Issue date May 2, 2006
- Renesas Technology Corp.
- Michio Komoda
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Circuit modification method
- Patent number 6,925,624
- Issue date Aug 2, 2005
- Renesas Technology Corp.
- Michio Komoda
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Semiconductor integrated circuit and test pattern generation method...
- Patent number 6,678,849
- Issue date Jan 13, 2004
- Mitsubishi Denki Kabushiki Kaisha
- Junya Shiraishi
- G01 - MEASURING TESTING
Information Patent Grant
Method of producing load for delay time calculation and recording m...
- Patent number 6,552,551
- Issue date Apr 22, 2003
- Mitsubishi Denki Kabushiki Kaisha
- Michio Komoda
- G01 - MEASURING TESTING
Information Patent Grant
Wiring data generation method and wiring data generation apparatus...
- Patent number 6,546,537
- Issue date Apr 8, 2003
- Mitsubishi Denki Kabushiki Kaisha
- Michio Komoda
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Gate delay calculation apparatus and method thereof using parameter...
- Patent number 6,510,404
- Issue date Jan 21, 2003
- Mitsubishi Denki Kabushiki Kaisha
- Shigeru Kuriyama
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Semiconductor integrated circuit device
- Patent number 6,292,043
- Issue date Sep 18, 2001
- Mitsubishi Denki Kabushiki Kaisha
- Junya Shiraishi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Test circuit and method for DC testing LSI capable of preventing si...
- Patent number 6,076,178
- Issue date Jun 13, 2000
- Mitsubishi Denki Kabushiki Kaisha
- Michio Komoda
- G01 - MEASURING TESTING
Information Patent Grant
Pipeline circuit with a test circuit with small circuit scale and a...
- Patent number 6,073,265
- Issue date Jun 6, 2000
- Mitsubishi Denki Kabushiki Kaisha
- Michio Komoda
- G01 - MEASURING TESTING
Information Patent Grant
Method for minimizing ground bounce during DC parametric tests usin...
- Patent number 6,000,050
- Issue date Dec 7, 1999
- Synopsys, Inc.
- Michio Komoda
- G01 - MEASURING TESTING
Information Patent Grant
Multiplier circuit with rounding-off function
- Patent number 5,619,440
- Issue date Apr 8, 1997
- Mitsubishi Denki Kabushiki Kaisha
- Michio Komoda
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Logic simulator
- Patent number 5,541,861
- Issue date Jul 30, 1996
- Mitsubishi Denki Kabushiki Kaisha
- Michio Komoda
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus for calculating delay time in logic functional blocks
- Patent number 5,515,291
- Issue date May 7, 1996
- Mitsubishi Denki Kabushiki Kaisha
- Naoko Omori
- G01 - MEASURING TESTING
Information Patent Grant
Apparatus for computing power consumption of MOS transistor logic f...
- Patent number 5,473,548
- Issue date Dec 5, 1995
- Mitsubishi Denki Kabushiki Kaisha
- Naoko Omori
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multiplier circuit and division circuit with a round-off function
- Patent number 5,444,647
- Issue date Aug 22, 1995
- Mitsubishi Denki Kabushiki Kaisha
- Michio Komoda
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Logic synthesizer
- Patent number 5,438,524
- Issue date Aug 1, 1995
- Mitsubishi Denki Kabushiki Kaisha
- Michio Komoda
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Logic simulator
- Patent number 5,379,232
- Issue date Jan 3, 1995
- Mitsubishi Denki Kabushiki Kaisha
- Michio Komoda
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
DELAY CALCULATION METHOD CAPABLE OF CALCULATING DELAY TIME WITH SMA...
- Publication number 20090043558
- Publication date Feb 12, 2009
- Renesas Technology Corp.
- Michio Komoda
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Clock forming method for semiconductor integrated circuit and progr...
- Publication number 20070094627
- Publication date Apr 26, 2007
- Renesas Technology Corp.
- Michio Komoda
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Automatic-arrangement-wiring apparatus for and program for performi...
- Publication number 20060043427
- Publication date Mar 2, 2006
- Renesas Technology Corp.
- Michio Komoda
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Delay calculation method capable of calculating delay time with sma...
- Publication number 20060015278
- Publication date Jan 19, 2006
- RENESAS TECHNOLOGY CORP.
- Michio Komoda
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Linear Filter circuit
- Publication number 20030098870
- Publication date May 29, 2003
- Michio Komoda
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Gate delay calculation apparatus and method thereof using parameter...
- Publication number 20020156610
- Publication date Oct 24, 2002
- Mitsubishi Denki Kabushiki Kaisha
- Shigeru Kuriyama
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method of formulating load model for glitch analysis and recording...
- Publication number 20020087294
- Publication date Jul 4, 2002
- Michio Komoda
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Delay time estimation method and recording medium storing estimatio...
- Publication number 20020077799
- Publication date Jun 20, 2002
- Michio Komoda
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Circuit modification method
- Publication number 20020060572
- Publication date May 23, 2002
- Michio Komoda
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method of producing load for delay time calculation and recording m...
- Publication number 20020036508
- Publication date Mar 28, 2002
- Michio Komoda
- G01 - MEASURING TESTING

Michio Komoda

Person

Patents Grantslast 30 patents

Delay calculation method capable of calculating delay time with sma...

Clock forming method for semiconductor integrated circuit and progr...

Delay time estimation method and recording medium storing estimatio...

Method of formulating load model for glitch analysis and recording...

Circuit modification method

Semiconductor integrated circuit and test pattern generation method...

Method of producing load for delay time calculation and recording m...

Wiring data generation method and wiring data generation apparatus...

Gate delay calculation apparatus and method thereof using parameter...

Semiconductor integrated circuit device

Test circuit and method for DC testing LSI capable of preventing si...

Pipeline circuit with a test circuit with small circuit scale and a...

Method for minimizing ground bounce during DC parametric tests usin...

Multiplier circuit with rounding-off function

Logic simulator

Apparatus for calculating delay time in logic functional blocks

Apparatus for computing power consumption of MOS transistor logic f...

Multiplier circuit and division circuit with a round-off function

Logic synthesizer

Logic simulator

Patents Applicationslast 30 patents

DELAY CALCULATION METHOD CAPABLE OF CALCULATING DELAY TIME WITH SMA...

Clock forming method for semiconductor integrated circuit and progr...

Automatic-arrangement-wiring apparatus for and program for performi...

Delay calculation method capable of calculating delay time with sma...

Linear Filter circuit

Gate delay calculation apparatus and method thereof using parameter...

Method of formulating load model for glitch analysis and recording...

Delay time estimation method and recording medium storing estimatio...

Circuit modification method

Method of producing load for delay time calculation and recording m...