Ming Sun

Person

Sunnyvale, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Methods and configuration for manufacturing flip chip contact (FCC)...
- Patent number 9,337,132
- Issue date May 10, 2016
- Alpha and Omega Semiconductor Incorporated
- Ming Sun
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Wafer level chip scale package and process of manufacture
- Patent number 8,981,464
- Issue date Mar 17, 2015
- Alpha and Omega Semiconductor Ltd.
- Tao Feng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and system for determining parameters of sinusoidal signals
- Patent number 8,972,215
- Issue date Mar 3, 2015
- Mitsubishi Electric Research Laboratories, Inc.
- Zafer Sahinoglu
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
Information Patent Grant
Method and apparatus for ultra thin wafer backside processing
- Patent number 8,846,532
- Issue date Sep 30, 2014
- Alpha and Omega Semiconductor Incorporated
- Tao Feng
- B32 - LAYERED PRODUCTS
Information Patent Grant
Multi-layer lead frame package and method of fabrication
- Patent number 8,815,649
- Issue date Aug 26, 2014
- Alpha & Omega Semiconductor Corporation
- Jun Lu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Wafer level chip scale package and process of manufacture
- Patent number 8,716,063
- Issue date May 6, 2014
- Alpha and Omega Semiconductor Ltd.
- Tao Feng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Conductive clip for semiconductor device package
- Patent number 8,680,658
- Issue date Mar 25, 2014
- Alpha and Omega Semiconductor Incorporated
- Lei Shi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Flip chip contact (FCC) power package
- Patent number 8,564,049
- Issue date Oct 22, 2013
- Alpha and Omega Semiconductor Incorporated
- Ming Sun
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multi-layer lead frame package and method of fabrication
- Patent number 8,513,784
- Issue date Aug 20, 2013
- Alpha and Omega Semiconductor Incorporated
- Jun Lu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for making solder-top enhanced semiconductor device of low p...
- Patent number 8,497,160
- Issue date Jul 30, 2013
- Alpha & Omega Semiconductor, Inc.
- François Hébert
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Wafer level chip scale packaging
- Patent number 8,426,960
- Issue date Apr 23, 2013
- Alpha & Omega Semiconductor, Inc.
- Ming Sun
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and apparatus for ultra thin wafer backside processing
- Patent number 8,361,903
- Issue date Jan 29, 2013
- Alpha and Omega Semiconductor Incorporated
- Tao Feng
- B24 - GRINDING POLISHING
Information Patent Grant
Packaging configurations for vertical electronic devices using cond...
- Patent number 8,330,264
- Issue date Dec 11, 2012
- Alpha and Omega Semiconductor Incorporated
- Ming Sun
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Solder-top enhanced semiconductor device for low parasitic impedanc...
- Patent number 8,264,084
- Issue date Sep 11, 2012
- Alpha & Omega Semiconductor, Inc.
- François Hébert
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Compact inductive power electronics package
- Patent number 8,217,748
- Issue date Jul 10, 2012
- Alpha and Omega Semiconductor Inc.
- Tao Feng
- Y10 - TECHNICAL SUBJECTS COVERED BY FORMER USPC
Information Patent Grant
Packaging configurations for vertical electronic devices using cond...
- Patent number 8,168,477
- Issue date May 1, 2012
- Alpha and Omega Semiconductor Incorporated
- Ming Sun
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Low profile flip chip power module and method of making
- Patent number 8,159,828
- Issue date Apr 17, 2012
- Alpha & Omega Semiconductor, Inc.
- Ming Sun
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Vertically packaged MOSFET and IC power devices as integrated modul...
- Patent number 8,124,453
- Issue date Feb 28, 2012
- Alpha & Omega Semiconductor, Ltd.
- Ming Sun
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Chip scale power converter package having an inductor substrate
- Patent number 8,058,960
- Issue date Nov 15, 2011
- Alpha and Omega Semiconductor Incorporated
- François Hébert
- Y10 - TECHNICAL SUBJECTS COVERED BY FORMER USPC
Information Patent Grant
Semiconductor package having a bridge plate connection
- Patent number 8,053,874
- Issue date Nov 8, 2011
- Alpha and Omega Semiconductor Incorporated
- Ming Sun
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Structure and method for self protection of power device
- Patent number 7,999,363
- Issue date Aug 16, 2011
- Alpha & Omega Semiconductor, Ltd.
- François Hébert
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Wafer level chip scale package and process of manufacture
- Patent number 7,955,893
- Issue date Jun 7, 2011
- Alpha and Omega Semiconductor, Ltd.
- Tao Feng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Dual flat non-leaded semiconductor package
- Patent number 7,951,651
- Issue date May 31, 2011
- Alpha and Omega Semiconductor Incorporated
- Kai Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Compact co-packaged semiconductor dies with elevation-adaptive inte...
- Patent number 7,906,375
- Issue date Mar 15, 2011
- Alpha and Omega Semiconductor Inc.
- Kai Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of making semiconductor package with plated connection
- Patent number 7,897,438
- Issue date Mar 1, 2011
- Alpha and Omega Semiconductor Incorporated
- Leeshawn Luo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor package having a bridged plate interconnection
- Patent number 7,884,469
- Issue date Feb 8, 2011
- Alpha and Omega Semiconductor Incorporated
- Lei Shi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Compact power semiconductor package and method with stacked inducto...
- Patent number 7,868,431
- Issue date Jan 11, 2011
- Alpha and Omega Semiconductor Incorporated
- Tao Feng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Packages for electronic devices implemented with laminated board wi...
- Patent number 7,838,977
- Issue date Nov 23, 2010
- Alpha & Omega Semiconductor, Ltd.
- Ming Sun
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Vertical packaged IC device modules with interconnected 3D laminate...
- Patent number 7,829,989
- Issue date Nov 9, 2010
- Alpha & Omega Semiconductor, Ltd.
- Ming Sun
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of fabricating a semiconductor device employing electroless...
- Patent number 7,811,904
- Issue date Oct 12, 2010
- Alpha and Omega Semiconductor Incorporated
- Tao Feng
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
FLIP CHIP CONTACT (FCC) POWER PACKAGE
- Publication number 20150102425
- Publication date Apr 16, 2015
- Ming Sun
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
WAFER LEVEL CHIP SCALE PACKAGE AND PROCESS OF MANUFACTURE
- Publication number 20140239383
- Publication date Aug 28, 2014
- ALPHA & OMEGA SEMICONDUCTOR, LTD.
- Tao Feng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD AND APPARATUS FOR ULTRA THIN WAFER BACKSIDE PROCESSING
- Publication number 20140076846
- Publication date Mar 20, 2014
- Tao Feng
- B32 - LAYERED PRODUCTS
Information Patent Application
MULTI-LAYER LEAD FRAME PACKAGE AND METHOD OF FABRICATION
- Publication number 20130302946
- Publication date Nov 14, 2013
- Jun Lu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for Making Solder-top Enhanced Semiconductor Device of Low P...
- Publication number 20120289001
- Publication date Nov 15, 2012
- Francois Hebert
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method and System for Determining Parameters of Sinusoidal Signals
- Publication number 20120253742
- Publication date Oct 4, 2012
- Zafer Sahinoglu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PACKAGING CONFIGURATIONS FOR VERTICAL ELECTRONIC DEVICES USING COND...
- Publication number 20120205803
- Publication date Aug 16, 2012
- Ming Sun
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
WAFER-LEVEL CHIP SCALE PACKAGING OF METAL-OXIDE-SEMICONDUCTOR FIELD...
- Publication number 20120202320
- Publication date Aug 9, 2012
- Tao Feng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method of Making a Low Profile Flip Chip Power Module
- Publication number 20120167384
- Publication date Jul 5, 2012
- Ming Sun
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Method and System for Estimating and Tracking Frequency and Phase A...
- Publication number 20120150468
- Publication date Jun 14, 2012
- Zafer Sahinoglu
- G01 - MEASURING TESTING
Information Patent Application
MULTI-LAYER LEAD FRAME PACKAGE AND METHOD OF FABRICATION
- Publication number 20110227205
- Publication date Sep 22, 2011
- Jun Lu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Vertically packaged MOSFET and IC power devices as integrated modul...
- Publication number 20110143499
- Publication date Jun 16, 2011
- Ming Sun
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
WAFER LEVEL CHIP SCALE PACKAGE AND PROCESS OF MANUFACTURE
- Publication number 20110108896
- Publication date May 12, 2011
- ALPHA & OMEGA SEMICONDUCTOR INCORPORATED
- TAO FENG
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Packaging configurations for vertical electronic devices using cond...
- Publication number 20110076808
- Publication date Mar 31, 2011
- Ming Sun
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Compact Co-packaged Semiconductor Dies with Elevation-adaptive Inte...
- Publication number 20100273294
- Publication date Oct 28, 2010
- Kai Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD AND APPARATUS FOR ULTRA THIN WAFER BACKSIDE PROCESSING
- Publication number 20100221431
- Publication date Sep 2, 2010
- Tao Feng
- B28 - WORKING CEMENT, CLAY, OR STONE
Information Patent Application
Compact Co-packaged Semiconductor Dies with Elevation-adaptive Inte...
- Publication number 20100032819
- Publication date Feb 11, 2010
- Kai Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CONDUCTIVE CLIP FOR SEMICONDUCTOR DEVICE PACKAGE
- Publication number 20090294934
- Publication date Dec 3, 2009
- ALPHA & OMEGA SEMICONDUCTOR, LTD.
- Lei Shi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DFN semiconductor package having reduced electrical resistance
- Publication number 20090258458
- Publication date Oct 15, 2009
- Xiaotian Zhang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR PACKAGE HAVING A BRIDGED PLATE INTERCONNECTION
- Publication number 20090236708
- Publication date Sep 24, 2009
- Lei Shi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DUAL FLAT NON-LEADED SEMICONDUCTOR PACKAGE
- Publication number 20090233403
- Publication date Sep 17, 2009
- Kai Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor package having a bridge plate connection
- Publication number 20090218673
- Publication date Sep 3, 2009
- Ming Sun
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
WAFER LEVEL CHIP SCALE PACKAGE AND PROCESS OF MANUFACTURE
- Publication number 20090194880
- Publication date Aug 6, 2009
- ALPHA & OMEGA SEMICONDUCTOR, LTD.
- Tao Feng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Compact Inductive Power Electronics Package
- Publication number 20090167477
- Publication date Jul 2, 2009
- Tao Feng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
WAFER LEVEL CHIP SCALE PACKAGING
- Publication number 20090160045
- Publication date Jun 25, 2009
- ALPHA & OMEGA SEMICONDUCTOR, LTD.
- Ming Sun
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Compact Power Semiconductor Package and Method with Stacked Inducto...
- Publication number 20090160595
- Publication date Jun 25, 2009
- Tao Feng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Solder-top Enhanced Semiconductor Device and Method for Low Parasit...
- Publication number 20090108456
- Publication date Apr 30, 2009
- Francois Hebert
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CO-PACKAGED HIGH-SIDE AND LOW-SIDE NMOSFETS FOR EFFICIENT DC-DC POW...
- Publication number 20090057869
- Publication date Mar 5, 2009
- ALPHA & OMEGA SEMICONDUCTOR, LTD.
- Francois Hebert
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method of forming ultra thin chips of power devices
- Publication number 20080242052
- Publication date Oct 2, 2008
- Tao Feng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Chip scale power converter package having an inductor substrate
- Publication number 20080238599
- Publication date Oct 2, 2008
- Francois Hebert
- H01 - BASIC ELECTRIC ELEMENTS

Person

Patents Grantslast 30 patents

Methods and configuration for manufacturing flip chip contact (FCC)...

Wafer level chip scale package and process of manufacture

Method and system for determining parameters of sinusoidal signals

Method and apparatus for ultra thin wafer backside processing

Multi-layer lead frame package and method of fabrication

Wafer level chip scale package and process of manufacture

Conductive clip for semiconductor device package

Flip chip contact (FCC) power package

Multi-layer lead frame package and method of fabrication

Method for making solder-top enhanced semiconductor device of low p...

Wafer level chip scale packaging

Method and apparatus for ultra thin wafer backside processing

Packaging configurations for vertical electronic devices using cond...

Solder-top enhanced semiconductor device for low parasitic impedanc...

Compact inductive power electronics package

Packaging configurations for vertical electronic devices using cond...

Low profile flip chip power module and method of making

Vertically packaged MOSFET and IC power devices as integrated modul...

Chip scale power converter package having an inductor substrate

Semiconductor package having a bridge plate connection

Structure and method for self protection of power device

Wafer level chip scale package and process of manufacture

Dual flat non-leaded semiconductor package

Compact co-packaged semiconductor dies with elevation-adaptive inte...

Method of making semiconductor package with plated connection

Semiconductor package having a bridged plate interconnection

Compact power semiconductor package and method with stacked inducto...

Packages for electronic devices implemented with laminated board wi...

Vertical packaged IC device modules with interconnected 3D laminate...

Method of fabricating a semiconductor device employing electroless...

Patents Applicationslast 30 patents

FLIP CHIP CONTACT (FCC) POWER PACKAGE

WAFER LEVEL CHIP SCALE PACKAGE AND PROCESS OF MANUFACTURE

METHOD AND APPARATUS FOR ULTRA THIN WAFER BACKSIDE PROCESSING

MULTI-LAYER LEAD FRAME PACKAGE AND METHOD OF FABRICATION

Method for Making Solder-top Enhanced Semiconductor Device of Low P...

Method and System for Determining Parameters of Sinusoidal Signals

PACKAGING CONFIGURATIONS FOR VERTICAL ELECTRONIC DEVICES USING COND...

WAFER-LEVEL CHIP SCALE PACKAGING OF METAL-OXIDE-SEMICONDUCTOR FIELD...

Method of Making a Low Profile Flip Chip Power Module

Method and System for Estimating and Tracking Frequency and Phase A...

MULTI-LAYER LEAD FRAME PACKAGE AND METHOD OF FABRICATION

Vertically packaged MOSFET and IC power devices as integrated modul...

WAFER LEVEL CHIP SCALE PACKAGE AND PROCESS OF MANUFACTURE

Packaging configurations for vertical electronic devices using cond...

Compact Co-packaged Semiconductor Dies with Elevation-adaptive Inte...

METHOD AND APPARATUS FOR ULTRA THIN WAFER BACKSIDE PROCESSING

Compact Co-packaged Semiconductor Dies with Elevation-adaptive Inte...

CONDUCTIVE CLIP FOR SEMICONDUCTOR DEVICE PACKAGE

DFN semiconductor package having reduced electrical resistance

SEMICONDUCTOR PACKAGE HAVING A BRIDGED PLATE INTERCONNECTION

DUAL FLAT NON-LEADED SEMICONDUCTOR PACKAGE

Semiconductor package having a bridge plate connection

WAFER LEVEL CHIP SCALE PACKAGE AND PROCESS OF MANUFACTURE

Compact Inductive Power Electronics Package

WAFER LEVEL CHIP SCALE PACKAGING

Compact Power Semiconductor Package and Method with Stacked Inducto...

Solder-top Enhanced Semiconductor Device and Method for Low Parasit...

CO-PACKAGED HIGH-SIDE AND LOW-SIDE NMOSFETS FOR EFFICIENT DC-DC POW...

Method of forming ultra thin chips of power devices

Chip scale power converter package having an inductor substrate