Patent Application
20080242052
This invention relates generally to the field of semiconductor device manufacturing. More specifically, the present invention is directed to methods to form ultra thin chips of power semiconductor devices, such as power Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) and Insulated Gate Bipolar Transistor (IGBT).
A general trend of modern day electronic product, as demanded by the market place, is product miniaturization with vastly increasing functionality. With no exception, the same trend also applies to the segment of power electronics. Hence, in the area of power electronics there has been an ongoing need of product miniaturization concurrent with the other requirements of efficient heat dissipation and electromagnetic interference/radio frequency interference (EMI/RFI) shielding prominent in power electronics.
As it offers advantages of bulk device electrical resistance reduction, bulk device thermal stress reduction and die stacking while maintaining low profile, the ability of making thin, less than about 10 mils, chips of power semiconductor devices is very desirable in the semiconductor industry. This is especially important in cases where an epitaxial layer has to be grown as the semiconductor bulk for High Voltage (HV) application due to high cost of thick epitaxial layers. This is because:
In U.S. Pat. No. 6,162,702, entitled “self-supported ultra thin silicon wafer process” Dec. 19, 2000, by Morcom et al. and assigned to Intersil Corporation, a Silicon wafer has numerous ultra thin central portions that are supported by a circumferential rim of thicker silicon was described. The central regions are thinned by conventional methods using conventional removal apparatus. As an alternative method, the central regions can also be etched out using a photoresist mask or a combination of a photoresist mask and a hard mask.
In U.S. Pat. No. 6,884,717, entitled “stiffened backside fabrication for microwave radio frequency wafers” Apr. 26, 2005, by Desalvo et al, an etching based semiconductor wafer thinning method was described as an improved alternative to grinding and polishing wafer thinning. The thinned wafer includes a structurally enhancing wafer backside grid array of original wafer thickness with grid cells surrounding individual thinned wafer areas for improvement of the strength and physical rigidity of the thinned wafer. Preferably the grid array is supplemented with an additional, wafer peripheral, backside ring also of original wafer thickness. Ability to avoid a wafer front side mounting during thinning accomplishment, fast etching, reduced wafer breakage, enhanced wafer strength and improved wafer handling achieved with the disclosed thinning arrangement all contribute to achieved advantages over conventional wafer thinning.
In US patent application 20050236693, entitled “wafer stabilization device and associated production method” Oct. 27, 2005, by Kroninger, Werner et al., a stabilization device and method were described for stabilizing a thin film wafer. The thin wafer is fixed and oriented in planar fashion. The stabilization device is a profiled ring arranged on the periphery of the wafer and is intimately connected thereto. The stabilization device and wafer are connected via negative pressure or by means of an adhesive having high thermal stability. The wafer and device are formed from similar semiconductor materials and have the same outline contour. The stabilization device remains on the wafer during process steps in the course of production and processing of the wafer.
U.S. Pat. No. 7,115,485 is entitled “method for processing wafer” Oct. 3, 2006, by Priewasser and is assigned to Disco Corporation (Tokyo, Japan). To facilitate handling a thin wafer during processing, a protective member is stuck through an adhesive agent to an outer-peripheral surplus region of a front surface of the wafer, the region being formed with no individual devices, and a back surface of the wafer is ground in a state where the whole front surface of the wafer is supported by the protective member. Since an outer periphery of the wafer is reinforced by the protective member, the wafer can be easily handled even after having been thinned by the grinding.
A method of making complete ultra thin chips of power semiconductor devices is proposed. Starting from a semiconductor wafer of an original thickness and with pre-fabricated front-side devices, the method includes:
In an embodiment of forming the ohmic contact, the method includes:
In another embodiment of forming the ohmic contact, the method includes:
In yet another embodiment of forming the ohmic contact, the method includes:
In yet another embodiment of forming the ohmic contact, the method includes probing and marking the wafer front-side to distinguish functional from defective devices. Owing to a stepped topography of the wafer back-side resulting from the thinning of only its central portion, the method further uses a step-profiled chuck matching and supporting the wafer back-side topography to prevent its breakage during wafer probing. The step-profiled chuck can be further provided with vacuum through ports on its top surface to strengthen its holding power of the wafer.
In a more specific embodiment, separating and collecting the pre-fabricated devices further includes:
In a more specific alternative embodiment, bonding the wafer back-side onto a dicing tape in a release way is done by:
In a more specific embodiment, separating the pre-fabricated devices from one another and from the wafer periphery is done by:
In a more specific alternative embodiment, separating and collecting the pre-fabricated devices further includes:
For separating the central portion from the peripheral portion of the wafer, a power laser can be employed to traverse a demarcation contour between the wafer central portion and its peripheral portion. Alternatively, a mechanical cutting head can be used in lieu of the power laser. Separating each of the pre-fabricated devices can be done by mechanically dicing apart, with a dicing depth slightly larger than the wafer thickness, the pre-fabricated devices from the wafer.
In a more specific alternative embodiment, separating and collecting the pre-fabricated devices can be done as follows:
These aspects of the present invention and their numerous embodiments are further made apparent, in the remainder of the present description, to those of ordinary skill in the art.
In order to more fully describe numerous embodiments of the present invention, reference is made to the accompanying drawings. However, these drawings are not to be considered limitations in the scope of the invention, but are merely illustrative.
The description above and below plus the drawings contained herein merely focus on one or more currently preferred embodiments of the present invention and also describe some exemplary optional features and/or alternative embodiments. The description and drawings are presented for the purpose of illustration and, as such, are not limitations of the present invention. Thus, those of ordinary skill in the art would readily recognize variations, modifications, and alternatives. Such variations, modifications and alternatives should be understood to be also within the scope of the present invention.
Next, STEP IIIa, called central portion back grinding, produces a substantially thinned down central portion of the wafer vertically opposing the fabricated devices 14. STEP IIIa also leaves a peripheral portion of original thickness, called edge ring 78, for structurally supporting the central portion against breakage from subsequent process handling. This will be presently seen. The central region can be thinned by conventional mechanical methods like wafer grinding and polishing. As an alternative, the central portion can also be chemically etched thin using a photoresist mask or a combination of a photoresist mask and a hard mask. In practice, the central portion can be thinned down to a thickness of about 2˜4 mils. Notice that, just before the operation to thin the central portion, a UV-releasable dicing tape 19 is adhered to the device side of the wafer as a protective cushion. The use of UV-releasable dicing tape 19 facilitates a later tape removal/transfer following a UV (Ultra Violet) irradiation of the dicing tape. The underlying mechanism is a reduction of tackiness upon UV irradiation.
In STEP IVa, called back side clean and etch, the front-side of the wafer is protected by the UV-releasable dicing tape 19 while the back-side of the wafer is chemically cleaned and etched in preparation for receiving a metallic ohmic contact thereto. This is important as the wafer back-side must be made free of dirt and oxides for a good ohmic contact. For power semiconductor devices, back-side metal deposition is usually part of the device requirement.
In STEP Va, called back metal deposition, the now cleaned and etched back-side of the wafer is deposited with a back metal 18 suitable for forming an ohmic contact thereto. Notice that, as high temperatures are typically encountered in a metal deposition process (vacuum deposition chamber temperature is usually at least 100-150 deg C.), the UV-releasable dicing tape 19 has been removed from the wafer before back metal deposition. Otherwise the following problems could take place:
The dicing tape may not endure the high process temperature of metal deposition, or the dicing tape may outgas in the vacuum deposition chamber and affects the quality of the ohmic contact.
The back metal deposition approaches include evaporation and sputtering.
As an option, STEP Va can be followed by a STEP VIa called wafer probing. Here, the fabricated devices 14 on the front-side of the wafer are probed and marked to distinguish functional from defective devices. Some related important next level detail will be presently described in
In STEP VIIa, called laser cutting, the front-side of the wafer is temporarily bonded onto a UV-releasable dicing tape one 20 with the periphery of the UV-releasable dicing tape one 20 fixed by a dicing frame 22. The dicing frame 22 together with the outer edge of the UV-releasable dicing tape one 20 are then affixed onto a chuck (not shown here for simplicity of presentation). The central portion of the wafer together with the UV-releasable dicing tape one 20 are then separated from the peripheral edge ring 78 of the wafer by traversing a demarcation contour between the central portion and the edge ring 78 with a power laser beam 24 to effect the separation.
In STEP VIIIa, called tape transfer and dicing, the now separated central portion of the back-side of the wafer is first bonded onto a dicing tape two 26 also in a way allowing future release of the wafer there from. With the outer edge of the dicing tape two 26 fixed by a dicing frame 22, release the UV-releasable dicing tape one 20 from the wafer front-side so as to effect a tape transfer. The dicing frame 22 together with the outer edge of the dicing tape two 26 are then affixed onto a chuck (not shown here for simplicity of presentation). The individual ultra thin power device chips 30 are then diced apart for collection with dicing streaks 28 produced by a corresponding dicing saw. The dicing streaks 28 should be slightly deeper than the wafer thickness for an effective device separation. Alternatively, the individual ultra thin power device chips 30 can be separated for collection with a correspondingly traversing laser beam. If a laser dicing machine with capability of dicing from the wafer back-side is employed, STEP VIIa to remove the edge ring 78 can be omitted. While not specifically illustrated here, the individual ultra thin power device chips 30 can be collected with a traversing vacuum pick up head, for example.
As illustrated in
The process as illustrated in
Next, STEP IIIb, called central portion back grinding, produces a substantially thinned down central portion of the wafer vertically opposing the fabricated devices 14 and leaves a peripheral portion of original thickness, called edge ring 78, for structural support just like the previous STEP IIIa.
STEPS IVb & Vb, when taken together, serve to make an ohmic contact to the back-side of the wafer with a back metal 18 just like STEPS IVa & Va taken together. Like before, the UV-releasable dicing tape 19 has been removed from the wafer before deposition of the back metal 18. STEPS IVb & Vb encompass the following alternative procedures for making the ohmic contact:
Alternative procedure one:
Except for using the low cost float zone semiconductor wafer 50, the remaining steps STEP VIb wafer probing, STEP VIIb laser cutting and STEP VIIIb dicing of
During the next STEP IIc, called removing backing plate and inverting wafer, the backing plate 74 is removed and the bonded assembly of wafer, single-sided dicing tape 70 and dicing frame 22 is inverted to expose the fabricated devices 14 at the top.
During the next STEP IIIc, called wafer dicing on special chuck, a step-profiled chuck 60 matching and supporting the stepped back-side topography of the single-sided dicing tape 70 is placed beneath the bonded assembly of wafer, single-sided dicing tape 70 and dicing frame 22 to support it against wafer breakage during subsequent processing steps. While not shown here to avoid obscuring details, the step-profiled chuck 60 can further include numerous vacuum ports on its top surface to strengthen its holding power of the single-sided dicing tape 70. With the outer edge of the single-sided dicing tape 70 fixed with the dicing frame 22, the fabricated devices 14 are then mechanically diced apart, with a dicing depth slightly larger than the thickness of wafer central portion, from one another and from the edge ring 78. This is illustrated with the numerous mechanical dicing streaks 28 traversing along scribe lines separating the fabricated devices 14 and the edge ring 78. Notice that the individual fabricated devices 14 and the edge ring 78 are still bonded to the single-sided dicing tape 70.
The next STEP IVc, called removing edge ring, is an optional step. With the diced wafer bonded on single-sided dicing tape 70 and the single-sided dicing tape 70 held by dicing frame 22, the separated edge ring 78 is removed from the single-sided dicing tape 70. While not essential, STEP IVc does produce a substantially flat wafer front-side topography facilitating the later pickup of individual fabricated devices 14 there from.
Finally in STEP Vc, called picking up and collecting individual pre-fabricated devices, the individual ultra thin power device chips 30 are picked up from the single-sided dicing tape 70 and collected under sufficient mechanical force from a vacuum picking up head 80. A back pushing pin 82, opposing the vacuum picking up head 80, is applied below the dicing tape to facilitate the device pick-up.
During the next STEP IId, called inverting and dicing wafer on ordinary chuck, the bonded assembly of wafer, backing plate, double-sided dicing tape 90 and dicing frame 22 is simply inverted to expose the fabricated devices 14 at the top. Except for the usage of a flat chuck 61, the rest of STEP IId is the same as STEP IIIc before. This is due to the presence of the bonded backing plate 74 at the thinned out wafer central portion making up for a flat bottom topography now. After that the separated wafer edge ring and the backing plate are removed from the dicing tape. The remaining STEP IIId and STEP IVd are respectively the same as STEP IVc and STEP Vc of
While the description above contains many specificities, these specificities should not be constructed as accordingly limiting the scope of the present invention but as merely providing illustrations of numerous presently preferred embodiments of this invention. For example, while the present invention is illustrated for ultra thin chips of power semiconductor devices, the present invention is equally applicable to many other types of semiconductor devices as well—such as digital, analog and RF devices.
Throughout the description and drawings, numerous exemplary embodiments were given with reference to specific configurations. It will be appreciated by those of ordinary skill in the art that the present invention can be embodied in numerous other specific forms and those of ordinary skill in the art would be able to practice such other embodiments without undue experimentation. The scope of the present invention, for the purpose of the present patent document, is hence not limited merely to the specific exemplary embodiments of the foregoing description, but rather is indicated by the following claims. Any and all modifications that come within the meaning and range of equivalents within the claims are intended to be considered as being embraced within the spirit and scope of the present invention.
