Minh Van Ngo

Person

Union City, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Gap-filling with uniform properties
- Patent number 8,415,256
- Issue date Apr 9, 2013
- Alexander Nickel
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for forming a semiconducting layer with improved gap filling...
- Patent number 8,133,801
- Issue date Mar 13, 2012
- Spansion LLC
- Rinji Sugino
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming a metal gate structure with tuning of work functi...
- Patent number 7,071,086
- Issue date Jul 4, 2006
- Advanced Micro Devices, Inc.
- Christy Woo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Copper damascene with low-k capping layer and improved electromigra...
- Patent number 6,989,601
- Issue date Jan 24, 2006
- Advanced Micro Devices, Inc.
- Minh van Ngo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for forming nitride capped Cu lines with reduced hillock for...
- Patent number 6,764,951
- Issue date Jul 20, 2004
- Advanced Micro Devices, Inc.
- Minh van Ngo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
METHOD FOR REDUCING STRESS-INDUCED VOIDS FOR 0.25-μM AND SMA...
- Patent number 6,492,258
- Issue date Dec 10, 2002
- Advanced Micro Devices, Inc.
- Minh Van Ngo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Forming an encapsulating layer after deposition of a dielectric com...
- Patent number 6,472,336
- Issue date Oct 29, 2002
- Advanced Micro Devices, Inc.
- Suzette K. Pangrle
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Grant
Method of manufacturing a semiconductor device with improved line w...
- Patent number 6,429,141
- Issue date Aug 6, 2002
- Advanced Micro Devices, Inc.
- Minh Van Ngo
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
Sub-cap and method of manufacture therefor in integrated circuit ca...
- Patent number 6,406,996
- Issue date Jun 18, 2002
- Advanced Micro Devices, Inc.
- Joffre F. Bernard
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for reducing stress-induced voids for 0.25mμ and smal...
- Patent number 6,329,718
- Issue date Dec 11, 2001
- Advanced Micro Devices, Inc.
- Minh Van Ngo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming a silicon bottom anti-reflective coating with red...
- Patent number 6,297,148
- Issue date Oct 2, 2001
- Advanced Micro Devices, Inc.
- Paul Besser
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming high density capping layers for copper interconne...
- Patent number 6,153,523
- Issue date Nov 28, 2000
- Advanced Micro Devices, Inc.
- Minh Van Ngo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Gate pattern formation using a bottom anti-reflective coating
- Patent number 5,963,841
- Issue date Oct 5, 1999
- Advanced Micro Devices, Inc.
- Olov B. Karlsson
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
DAMASCENE PROCESSING EMPLOYING LOW SI-SION ETCH STOP LAYER/ARC
- Publication number 20020123217
- Publication date Sep 5, 2002
- Ramkumar Subramanian
- H01 - BASIC ELECTRIC ELEMENTS

Minh Van Ngo

Person

Patents Grantslast 30 patents

Gap-filling with uniform properties

Method for forming a semiconducting layer with improved gap filling...

Method of forming a metal gate structure with tuning of work functi...

Copper damascene with low-k capping layer and improved electromigra...

Method for forming nitride capped Cu lines with reduced hillock for...

METHOD FOR REDUCING STRESS-INDUCED VOIDS FOR 0.25-&#x03BC;M AND SMA...

Forming an encapsulating layer after deposition of a dielectric com...

Method of manufacturing a semiconductor device with improved line w...

Sub-cap and method of manufacture therefor in integrated circuit ca...

Method for reducing stress-induced voids for 0.25m&#x03BC; and smal...

Method of forming a silicon bottom anti-reflective coating with red...

Method of forming high density capping layers for copper interconne...

Gate pattern formation using a bottom anti-reflective coating

Patents Applicationslast 30 patents

DAMASCENE PROCESSING EMPLOYING LOW SI-SION ETCH STOP LAYER/ARC

METHOD FOR REDUCING STRESS-INDUCED VOIDS FOR 0.25-μM AND SMA...

Method for reducing stress-induced voids for 0.25mμ and smal...