Moez Cherif

Person

San Jose, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Constraints and objectives used in synthesis of a network-on-chip (...
- Patent number 12,135,928
- Issue date Nov 5, 2024
- ARTERIS, INC.
- Benoit De Lescure
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Incremental topology modification of a network-on-chip
- Patent number 11,956,127
- Issue date Apr 9, 2024
- ARTERIS, INC.
- Benoit De Lescure
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Constraints and objectives used in synthesis of a network-on-chip (...
- Patent number 11,836,427
- Issue date Dec 5, 2023
- ARTERIS, INC.
- Benoit De Lescure
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Quality metrics for optimization tasks in generation of a network
- Patent number 11,784,909
- Issue date Oct 10, 2023
- ARTERIS, INC.
- Benoit de Lescure
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
System and method to generate a network-on-chip (NoC) description u...
- Patent number 11,748,535
- Issue date Sep 5, 2023
- ARTERIS, INC.
- Moez Cherif
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for synthesis of a network-on-chip for deadlock-f...
- Patent number 11,665,776
- Issue date May 30, 2023
- ARTERIS, INC.
- Moez Cherif
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-phase topology synthesis of a network-on-chip (NoC)
- Patent number 11,657,203
- Issue date May 23, 2023
- ARTERIS, INC.
- Moez Cherif
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for generation of quality metrics for optimizatio...
- Patent number 11,601,357
- Issue date Mar 7, 2023
- ARTERIS, INC.
- Moez Cherif
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
System and method for generating and using physical roadmaps in net...
- Patent number 11,558,259
- Issue date Jan 17, 2023
- ARTERIS, INC.
- Moez Cherif
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Synthesis of a network-on-chip (NoC) using performance constraints...
- Patent number 11,449,655
- Issue date Sep 20, 2022
- ARTERIS, INC.
- Moez Cherif
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Physically aware topology synthesis of a network
- Patent number 11,121,933
- Issue date Sep 14, 2021
- ARTERIS, INC.
- Moez Cherif
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for incremental topology synthesis of a network-o...
- Patent number 10,990,724
- Issue date Apr 27, 2021
- ARTERIS, INC.
- Moez Cherif
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
INCREMENTAL TOPOLOGY MODIFICATION OF A NETWORK-ON-CHIP
- Publication number 20240259274
- Publication date Aug 1, 2024
- Arteris, Inc
- Benoit De LESCURE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CONSTRAINTS AND OBJECTIVES USED IN SYNTHESIS OF A NETWORK-ON-CHIP (...
- Publication number 20240220692
- Publication date Jul 4, 2024
- Arteris, Inc
- Benoit de LESCURE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM AND METHOD TO GENERATE A NETWORK-ON-CHIP (NoC) DESCRIPTION U...
- Publication number 20240211666
- Publication date Jun 27, 2024
- Arteris, Inc
- Moez CHERIF
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
QUALITY METRICS FOR OPTIMIZATION TASKS IN GENERATION OF A NETWORK
- Publication number 20230155919
- Publication date May 18, 2023
- Arteris, Inc
- Benoit de LESCURE
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
SYNTHESIS OF A NETWORK-ON-CHIP (NoC) FOR INSERTION OF PIPELINE STAGES
- Publication number 20230105677
- Publication date Apr 6, 2023
- Arteris, Inc
- Benoit de LESCURE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM AND METHOD FOR DEADLOCK DETECTION IN NETWORK-ON-CHIP (NoC) H...
- Publication number 20230096061
- Publication date Mar 30, 2023
- Arteris, Inc
- Benoit de LESCURE
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
CONSTRAINTS AND OBJECTIVES USED IN SYNTHESIS OF A NETWORK-ON-CHIP (...
- Publication number 20230013697
- Publication date Jan 19, 2023
- Arteris, Inc
- Benoit de LESCURE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INCREMENTAL TOPOLOGY MODIFICATION OF A NETWORK-ON-CHIP
- Publication number 20220294704
- Publication date Sep 15, 2022
- Arteris, Inc
- Benoit De LESCURE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYNTHESIS OF A NETWORK-ON-CHIP (NoC) USING PERFORMANCE CONSTRAINTS...
- Publication number 20220210030
- Publication date Jun 30, 2022
- Arteris, Inc
- Moez CHERIF
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM AND METHOD FOR GENERATION OF QUALITY METRICS FOR OPTIMIZATIO...
- Publication number 20220200889
- Publication date Jun 23, 2022
- Arteris, Inc
- Moez CHERIF
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
SYSTEM AND METHOD TO GENERATE A NETWORK-ON-CHIP (NoC) DESCRIPTION U...
- Publication number 20220188490
- Publication date Jun 16, 2022
- Arteris, Inc
- Moez CHERIF
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TOPOLOGY SYNTHESIS OF A NETWORK-ON-CHIP (NoC)
- Publication number 20210409284
- Publication date Dec 30, 2021
- Arteris, Inc
- Moez CHERIF
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM AND METHOD FOR SYNTHESIS OF A NETWORK-ON-CHIP FOR DEADLOCK-F...
- Publication number 20210204360
- Publication date Jul 1, 2021
- Arteris, Inc
- Moez CHERIF
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
SYSTEM AND METHOD FOR GENERATING AND USING PHYSICAL ROADMAPS IN NET...
- Publication number 20210203557
- Publication date Jul 1, 2021
- Arteris, Inc
- Moez CHERIF
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
MULTI-PHASE TOPOLOGY SYNTHESIS OF A NETWORK-ON-CHIP (NoC)
- Publication number 20210200928
- Publication date Jul 1, 2021
- Arteris, Inc
- Moez CHERIF
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PHYSICALLY AWARE TOPOLOGY SYNTHESIS OF A NETWORK
- Publication number 20210203564
- Publication date Jul 1, 2021
- Arteris, Inc
- Moez CHERIF
- G06 - COMPUTING CALCULATING COUNTING

Moez Cherif

Person

Patents Grantslast 30 patents

Constraints and objectives used in synthesis of a network-on-chip (...

Incremental topology modification of a network-on-chip

Constraints and objectives used in synthesis of a network-on-chip (...

Quality metrics for optimization tasks in generation of a network

System and method to generate a network-on-chip (NoC) description u...

System and method for synthesis of a network-on-chip for deadlock-f...

Multi-phase topology synthesis of a network-on-chip (NoC)

System and method for generation of quality metrics for optimizatio...

System and method for generating and using physical roadmaps in net...

Synthesis of a network-on-chip (NoC) using performance constraints...

Physically aware topology synthesis of a network

System and method for incremental topology synthesis of a network-o...

Patents Applicationslast 30 patents

INCREMENTAL TOPOLOGY MODIFICATION OF A NETWORK-ON-CHIP

CONSTRAINTS AND OBJECTIVES USED IN SYNTHESIS OF A NETWORK-ON-CHIP (...

SYSTEM AND METHOD TO GENERATE A NETWORK-ON-CHIP (NoC) DESCRIPTION U...

QUALITY METRICS FOR OPTIMIZATION TASKS IN GENERATION OF A NETWORK

SYNTHESIS OF A NETWORK-ON-CHIP (NoC) FOR INSERTION OF PIPELINE STAGES

SYSTEM AND METHOD FOR DEADLOCK DETECTION IN NETWORK-ON-CHIP (NoC) H...

CONSTRAINTS AND OBJECTIVES USED IN SYNTHESIS OF A NETWORK-ON-CHIP (...

INCREMENTAL TOPOLOGY MODIFICATION OF A NETWORK-ON-CHIP

SYNTHESIS OF A NETWORK-ON-CHIP (NoC) USING PERFORMANCE CONSTRAINTS...

SYSTEM AND METHOD FOR GENERATION OF QUALITY METRICS FOR OPTIMIZATIO...

SYSTEM AND METHOD TO GENERATE A NETWORK-ON-CHIP (NoC) DESCRIPTION U...

TOPOLOGY SYNTHESIS OF A NETWORK-ON-CHIP (NoC)

SYSTEM AND METHOD FOR SYNTHESIS OF A NETWORK-ON-CHIP FOR DEADLOCK-F...

SYSTEM AND METHOD FOR GENERATING AND USING PHYSICAL ROADMAPS IN NET...

MULTI-PHASE TOPOLOGY SYNTHESIS OF A NETWORK-ON-CHIP (NoC)

PHYSICALLY AWARE TOPOLOGY SYNTHESIS OF A NETWORK