Mustafa Badaroglu

Person

Leuven, BE

People

Patents Grantslast 30 patents

Information Patent Grant
Trench power rail in cell circuits to reduce resistance and related...
- Patent number 12,074,109
- Issue date Aug 27, 2024
- QUALCOMM Incorporated
- Mustafa Badaroglu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Digital compute in memory
- Patent number 12,019,905
- Issue date Jun 25, 2024
- QUALCOMM Incorporated
- Zhongze Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Digital compute-in-memory (DCIM) bit cell circuit layouts and DCIM...
- Patent number 11,581,037
- Issue date Feb 14, 2023
- QUALCOMM Incorporated
- Xiaonan Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hybrid metallization interconnects for power distribution and signa...
- Patent number 11,121,075
- Issue date Sep 14, 2021
- QUALCOMM Incorporated
- Mustafa Badaroglu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming gate of semiconductor device and semiconductor de...
- Patent number 10,607,896
- Issue date Mar 31, 2020
- Imec VZW
- Lars-Ake Ragnarsson
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuits employing a field gate(s) without dielectric la...
- Patent number 10,411,091
- Issue date Sep 10, 2019
- QUALCOMM Incorporated
- Mustafa Badaroglu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrating a gate-all-around (GAA) field-effect transistor(s) (FET...
- Patent number 10,332,881
- Issue date Jun 25, 2019
- QUALCOMM Incorporated
- Mustafa Badaroglu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Standard cell circuits employing voltage rails electrically coupled...
- Patent number 10,283,526
- Issue date May 7, 2019
- QUALCOMM Incorporated
- John Jianhong Zhu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Nanowire device with reduced parasitics
- Patent number 10,157,992
- Issue date Dec 18, 2018
- QUALCOMM Incorporated
- Mustafa Badaroglu
- B82 - NANO-TECHNOLOGY
Information Patent Grant
Selectively recessing trench isolation in three-dimensional (3D) tr...
- Patent number 10,109,646
- Issue date Oct 23, 2018
- QUALCOMM Incorporated
- Mustafa Badaroglu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Standard cell circuits employing high aspect ratio voltage rails fo...
- Patent number 10,090,244
- Issue date Oct 2, 2018
- QUALCOMM Incorporated
- Jeffrey Junhao Xu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Semiconductor device having a gap defined therein
- Patent number 10,079,293
- Issue date Sep 18, 2018
- QUALCOMM Incorporated
- Jeffrey Junhao Xu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Vertically stacked nanowire field effect transistors
- Patent number 10,043,796
- Issue date Aug 7, 2018
- QUALCOMM Incorporated
- Vladimir Machkaoutsan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Nanowire channel structures of continuously stacked nanowires for c...
- Patent number 10,032,678
- Issue date Jul 24, 2018
- QUALCOMM Incorporated
- Jeffrey Junhao Xu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Minimum track standard cell circuits for reduced area
- Patent number 9,985,014
- Issue date May 29, 2018
- QUALCOMM Incorporated
- Jeffrey Junhao Xu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Contact wrap around structure
- Patent number 9,953,979
- Issue date Apr 24, 2018
- QUALCOMM Incorporated
- Jeffrey Junhao Xu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device having a gap defined therein
- Patent number 9,871,121
- Issue date Jan 16, 2018
- QUALCOMM Incorporated
- Jeffrey Junhao Xu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Adjacent device isolation
- Patent number 9,824,936
- Issue date Nov 21, 2017
- QUALCOMM Incorporated
- Vladimir Machkaoutsan
- B82 - NANO-TECHNOLOGY
Information Patent Grant
Self-aligned structure
- Patent number 9,799,560
- Issue date Oct 24, 2017
- QUALCOMM Incorporated
- Stanley Seungchul Song
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Self-aligned metal cut and via for back-end-of-line (BEOL) processe...
- Patent number 9,793,164
- Issue date Oct 17, 2017
- QUALCOMM Incorporated
- Vladimir Machkaoutsan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Magnetic tunnel junction (MTJ) device array
- Patent number 9,728,718
- Issue date Aug 8, 2017
- QUALCOMM Incorporated
- Vladimir Machkaoutsan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Reduced height M1 metal lines for local on-chip routing
- Patent number 9,666,481
- Issue date May 30, 2017
- QUALCOMM Incorporated
- Stanley Seungchul Song
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Magnetic tunnel junction (MTJ) device array
- Patent number 9,570,509
- Issue date Feb 14, 2017
- QUALCOMM Incorporated
- Vladimir Machkaoutsan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and apparatus for source-drain junction formation in a FinFE...
- Patent number 9,564,518
- Issue date Feb 7, 2017
- QUALCOMM Incorporated
- Vladimir Machkaoutsan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Adjacent device isolation
- Patent number 9,502,414
- Issue date Nov 22, 2016
- QUALCOMM Incorporated
- Vladimir Machkaoutsan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Sub-fin device isolation
- Patent number 9,496,181
- Issue date Nov 15, 2016
- QUALCOMM Incorporated
- Stanley Seungchul Song
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Reduced height M1 metal lines for local on-chip routing
- Patent number 9,349,686
- Issue date May 24, 2016
- QUALCOMM Incorporated
- Stanley Seungchul Song
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Test circuit for testing through-silicon-vias in 3D integrated circ...
- Patent number 8,773,157
- Issue date Jul 8, 2014
- IMEC
- Mustafa Badaroglu
- G01 - MEASURING TESTING
Information Patent Grant
Devices comprising delay line for applying variable delay to clock...
- Patent number 8,233,579
- Issue date Jul 31, 2012
- IMEC
- Mustafa Badaroglu
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Method and apparatus for minimizing the influence of a digital sub-...
- Patent number 7,987,382
- Issue date Jul 26, 2011
- IMEC
- Mustafa Badaroglu
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
PORT LANDING-FREE LOW-SKEW SIGNAL DISTRIBUTION WITH BACKSIDE METALL...
- Publication number 20240096790
- Publication date Mar 21, 2024
- QUALCOMM Incorporated
- Mustafa Badaroglu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TRENCH POWER RAIL IN CELL CIRCUITS TO REDUCE RESISTANCE AND RELATED...
- Publication number 20230238325
- Publication date Jul 27, 2023
- QUALCOMM Incorporated
- Mustafa Badaroglu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ACCUMULATOR FOR DIGITAL COMPUTATION-IN-MEMORY ARCHITECTURES
- Publication number 20230115373
- Publication date Apr 13, 2023
- QUALCOMM Incorporated
- Mustafa BADAROGLU
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PARALLEL DEPTH-WISE PROCESSING ARCHITECTURES FOR NEURAL NETWORKS
- Publication number 20230065725
- Publication date Mar 2, 2023
- QUALCOMM Incorporated
- Mustafa BADAROGLU
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PARTIAL SUM MANAGEMENT AND RECONFIGURABLE SYSTOLIC FLOW ARCHITECTUR...
- Publication number 20230047364
- Publication date Feb 16, 2023
- QUALCOMM Incorporated
- Mustafa BADAROGLU
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FOLDING COLUMN ADDER ARCHITECTURE FOR DIGITAL COMPUTE IN MEMORY
- Publication number 20230031841
- Publication date Feb 2, 2023
- QUALCOMM Incorporated
- Mustafa BADAROGLU
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DIGITAL COMPUTE IN MEMORY
- Publication number 20230037054
- Publication date Feb 2, 2023
- QUALCOMM Incorporated
- Zhongze WANG
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HYBRID MACHINE LEARNING ARCHITECTURE WITH NEURAL PROCESSING UNIT AN...
- Publication number 20230025068
- Publication date Jan 26, 2023
- QUALCOMM Incorporated
- Mustafa BADAROGLU
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DIGITAL COMPUTE-IN-MEMORY (DCIM) BIT CELL CIRCUIT LAYOUTS AND DCIM...
- Publication number 20220392524
- Publication date Dec 8, 2022
- QUALCOMM Incorporated
- Xiaonan Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTEGRATED CIRCUITS EMPLOYING VARIED GATE TOPOGRAPHY BETWEEN AN ACT...
- Publication number 20200020688
- Publication date Jan 16, 2020
- QUALCOMM Incorporated
- Mustafa Badaroglu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUITS (ICS) MADE USING EXTREME ULTRAVIOLET (EUV) PATT...
- Publication number 20200006122
- Publication date Jan 2, 2020
- QUALCOMM Incorporated
- Mustafa Badaroglu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HYBRID METALLIZATION INTERCONNECTS FOR POWER DISTRIBUTION AND SIGNA...
- Publication number 20190295942
- Publication date Sep 26, 2019
- QUALCOMM Incorporated
- Mustafa BADAROGLU
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DIGITAL CURRENT MEASUREMENT FOR IN-SITU DEVICE MONITORING
- Publication number 20190107569
- Publication date Apr 11, 2019
- QUALCOMM Incorporated
- David Kidd
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
NANOWIRE DEVICE WITH REDUCED PARASITICS
- Publication number 20190067435
- Publication date Feb 28, 2019
- QUALCOMM Incorporated
- Mustafa Badaroglu
- B82 - NANO-TECHNOLOGY
Information Patent Application
SEMICONDUCTOR DEVICES EMPLOYING REDUCED AREA CONFORMAL CONTACTS TO...
- Publication number 20180212029
- Publication date Jul 26, 2018
- QUALCOMM Incorporated
- Jeffrey Junhao Xu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STANDARD CELL CIRCUITS EMPLOYING VOLTAGE RAILS ELECTRICALLY COUPLED...
- Publication number 20180175060
- Publication date Jun 21, 2018
- QUALCOMM Incorporated
- John Jianhong Zhu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR DEVICE HAVING A GAP DEFINED THEREIN
- Publication number 20180114848
- Publication date Apr 26, 2018
- Qualcomm Incorporated
- Jeffrey Junhao Xu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MINIMUM TRACK STANDARD CELL CIRCUITS FOR REDUCED AREA
- Publication number 20180076189
- Publication date Mar 15, 2018
- QUALCOMM Incorporated
- Jeffrey Junhao Xu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
STANDARD CELL CIRCUITS EMPLOYING HIGH ASPECT RATIO VOLTAGE RAILS FO...
- Publication number 20180033729
- Publication date Feb 1, 2018
- QUALCOMM Incorporated
- Jeffrey Junhao Xu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD OF FORMING GATE OF SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DE...
- Publication number 20170330801
- Publication date Nov 16, 2017
- IMEC vzw
- Lars-Ake Ragnarsson
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
VERTICALLY STACKED NANOWIRE FIELD EFFECT TRANSISTORS
- Publication number 20170221884
- Publication date Aug 3, 2017
- QUALCOMM Incorporated
- Vladimir Machkaoutsan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
NANOWIRE DEVICE WITH REDUCED PARASITICS
- Publication number 20170186846
- Publication date Jun 29, 2017
- QUALCOMM Incorporated
- Mustafa Badaroglu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SELF-ALIGNED METAL CUT AND VIA FOR BACK-END-OF-LINE (BEOL) PROCESSE...
- Publication number 20170140986
- Publication date May 18, 2017
- QUALCOMM Incorporated
- Vladimir Machkaoutsan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
NANOWIRE CHANNEL STRUCTURES OF CONTINUOUSLY STACKED NANOWIRES FOR C...
- Publication number 20170110374
- Publication date Apr 20, 2017
- QUALCOMM Incorporated
- Jeffrey Junhao Xu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
NANOWIRE CHANNEL STRUCTURES OF CONTINUOUSLY STACKED HETEROGENEOUS N...
- Publication number 20170110541
- Publication date Apr 20, 2017
- QUALCOMM Incorporated
- Jeffrey Junhao Xu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD AND APPARATUS FOR SOURCE-DRAIN JUNCTION FORMATION IN A FINFE...
- Publication number 20170104088
- Publication date Apr 13, 2017
- QUALCOMM Incorporated
- Vladimir MACHKAOUTSAN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MAGNETIC TUNNEL JUNCTION (MTJ) DEVICE ARRAY
- Publication number 20170104153
- Publication date Apr 13, 2017
- QUALCOMM Incorporated
- Vladimir Machkaoutsan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ADJACENT DEVICE ISOLATION
- Publication number 20170033020
- Publication date Feb 2, 2017
- QUALCOMM Incorporated
- Vladimir MACHKAOUTSAN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SELF-ALIGNED STRUCTURE
- Publication number 20160293485
- Publication date Oct 6, 2016
- QUALCOMM Incorporated
- Stanley Seungchul Song
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ADJACENT DEVICE ISOLATION
- Publication number 20160254261
- Publication date Sep 1, 2016
- QUALCOMM Incorporated
- Vladimir MACHKAOUTSAN
- H01 - BASIC ELECTRIC ELEMENTS

Mustafa Badaroglu

Person

Patents Grantslast 30 patents

Trench power rail in cell circuits to reduce resistance and related...

Digital compute in memory

Digital compute-in-memory (DCIM) bit cell circuit layouts and DCIM...

Hybrid metallization interconnects for power distribution and signa...

Method of forming gate of semiconductor device and semiconductor de...

Integrated circuits employing a field gate(s) without dielectric la...

Integrating a gate-all-around (GAA) field-effect transistor(s) (FET...

Standard cell circuits employing voltage rails electrically coupled...

Nanowire device with reduced parasitics

Selectively recessing trench isolation in three-dimensional (3D) tr...

Standard cell circuits employing high aspect ratio voltage rails fo...

Semiconductor device having a gap defined therein

Vertically stacked nanowire field effect transistors

Nanowire channel structures of continuously stacked nanowires for c...

Minimum track standard cell circuits for reduced area

Contact wrap around structure

Semiconductor device having a gap defined therein

Adjacent device isolation

Self-aligned structure

Self-aligned metal cut and via for back-end-of-line (BEOL) processe...

Magnetic tunnel junction (MTJ) device array

Reduced height M1 metal lines for local on-chip routing

Magnetic tunnel junction (MTJ) device array

Method and apparatus for source-drain junction formation in a FinFE...

Adjacent device isolation

Sub-fin device isolation

Reduced height M1 metal lines for local on-chip routing

Test circuit for testing through-silicon-vias in 3D integrated circ...

Devices comprising delay line for applying variable delay to clock...

Method and apparatus for minimizing the influence of a digital sub-...

Patents Applicationslast 30 patents

PORT LANDING-FREE LOW-SKEW SIGNAL DISTRIBUTION WITH BACKSIDE METALL...

TRENCH POWER RAIL IN CELL CIRCUITS TO REDUCE RESISTANCE AND RELATED...

ACCUMULATOR FOR DIGITAL COMPUTATION-IN-MEMORY ARCHITECTURES

PARALLEL DEPTH-WISE PROCESSING ARCHITECTURES FOR NEURAL NETWORKS

PARTIAL SUM MANAGEMENT AND RECONFIGURABLE SYSTOLIC FLOW ARCHITECTUR...

FOLDING COLUMN ADDER ARCHITECTURE FOR DIGITAL COMPUTE IN MEMORY

DIGITAL COMPUTE IN MEMORY

HYBRID MACHINE LEARNING ARCHITECTURE WITH NEURAL PROCESSING UNIT AN...

DIGITAL COMPUTE-IN-MEMORY (DCIM) BIT CELL CIRCUIT LAYOUTS AND DCIM...

INTEGRATED CIRCUITS EMPLOYING VARIED GATE TOPOGRAPHY BETWEEN AN ACT...

INTEGRATED CIRCUITS (ICS) MADE USING EXTREME ULTRAVIOLET (EUV) PATT...

HYBRID METALLIZATION INTERCONNECTS FOR POWER DISTRIBUTION AND SIGNA...

DIGITAL CURRENT MEASUREMENT FOR IN-SITU DEVICE MONITORING

NANOWIRE DEVICE WITH REDUCED PARASITICS

SEMICONDUCTOR DEVICES EMPLOYING REDUCED AREA CONFORMAL CONTACTS TO...

STANDARD CELL CIRCUITS EMPLOYING VOLTAGE RAILS ELECTRICALLY COUPLED...

SEMICONDUCTOR DEVICE HAVING A GAP DEFINED THEREIN

MINIMUM TRACK STANDARD CELL CIRCUITS FOR REDUCED AREA

STANDARD CELL CIRCUITS EMPLOYING HIGH ASPECT RATIO VOLTAGE RAILS FO...

METHOD OF FORMING GATE OF SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DE...

VERTICALLY STACKED NANOWIRE FIELD EFFECT TRANSISTORS

NANOWIRE DEVICE WITH REDUCED PARASITICS

SELF-ALIGNED METAL CUT AND VIA FOR BACK-END-OF-LINE (BEOL) PROCESSE...

NANOWIRE CHANNEL STRUCTURES OF CONTINUOUSLY STACKED NANOWIRES FOR C...

NANOWIRE CHANNEL STRUCTURES OF CONTINUOUSLY STACKED HETEROGENEOUS N...

METHOD AND APPARATUS FOR SOURCE-DRAIN JUNCTION FORMATION IN A FINFE...

MAGNETIC TUNNEL JUNCTION (MTJ) DEVICE ARRAY

ADJACENT DEVICE ISOLATION

SELF-ALIGNED STRUCTURE

ADJACENT DEVICE ISOLATION