Patent Application
20190107569
This disclosure relates generally to the field of digital current measurement, and, in particular, to digital current measurement for in-situ device monitoring.
Transistor production on wafers may result in undesirable process variations which degrade electronics performance. Thus, transistor characteristics, such as transistor current, need to be measured to assess process variations on the wafers. Current electronics designs may include special wafers which incorporate non-operational circuitry which measure transistor characteristics (e.g. transistor current) on the wafer. However, such special wafers cannot be sold since the non-operational circuitry prevents full functionality.
The following presents a simplified summary of one or more aspects of the present disclosure, in order to provide a basic understanding of such aspects. This summary is not an extensive overview of all contemplated features of the disclosure, and is intended neither to identify key or critical elements of all aspects of the disclosure nor to delineate the scope of any or all aspects of the disclosure. Its sole purpose is to present some concepts of one or more aspects of the disclosure in a simplified form as a prelude to the more detailed description that is presented later.
In one aspect, the disclosure provides a current measurement system for in-situ device. Accordingly, a method for digital current measurement for monitoring an in-situ device, the method including: using a transistor under test (TUT) to charge or discharge a capacitor; changing an oscillation state when a capacitor voltage of the capacitor crosses a threshold and turning OFF the TUT; discharging the capacitor using the TUT; commencing precharging the capacitor after detecting the capacitor reaches a transition voltage; commencing discharging the capacitor after a precharger time delay; sustaining a relaxation oscillator waveform, wherein the relaxation oscillator waveform is based on turning OFF and turning ON the TUT; and generating a digital representation of a TUT current, wherein the TUT current is associated with a relaxation oscillator period of the relaxation oscillator waveform.
In one example, the threshold is half of a maximum value of a drain voltage of the TUT. The method may further include using a conversion equation to convert the relaxation oscillator period to an inverse current of the TUT. In one example, the inverse current of the TUT is a reciprocal of the TUT current. The conversion equation may have the form of a linear equation. And, in one example, the conversion equation is as follows: Tosc=C ΔV I−1+tckt, wherein Tosc is the relaxation oscillator period, C ΔV is a slope of the conversion equation, and tckt is a circuit offset time due to a precharger time delay. C is a capacitance value of the capacitor and ΔV is the change of voltage of the capacitor. In one example, the conversion equation is based on a calibration process which uses a reference current or a circuit simulation model.
In one example, the in-situ device includes a plurality of negative channel metal oxide semiconductor (NMOS) transistors. And, the in-situ device may include a plurality of positive channel metal oxide semiconductor (PMOS) transistors. In one example, a precharger is used to precharge the capacitor.
Another aspect of the disclosure provides a measurement tile including: a transistor under test (TUT); a pulse generator to sustain a relaxation oscillator waveform with a relaxation oscillator period associated with an inverse current of the TUT; a capacitor coupled to the TUT; a precharger coupled to the capacitor and to the TUT, the precharger for charging the capacitor and the TUT for charging or discharging the capacitor, wherein the relaxation oscillator waveform is based on turning OFF and turning ON the TUT in accordance with discharging and charging the capacitor. In one example, the measurement tile further includes an output divider to output a modified relaxation oscillator waveform, wherein the modified relaxation oscillator waveform is the relaxation oscillator waveform with the relaxation oscillator period modified, and wherein the output divider is coupled to the capacitor. In one example, the modified relaxation oscillator waveform is inputted to a counter, the counter to output a digital current measurement of the TUT.
In one example, the pulse generator includes a combinational logic to provide a clock input in accordance with the TUT; a flip flop to receive the clock input; and an inverter coupled to the flip flop to form an inverting feedback loop such that the output state of the flip flop changes each time the clock on the flip flop is pulsed. In one example, the inverting feedback loop sustains the relaxation oscillator waveform in accordance with an ON/OFF state of the TUT. In one example, a drain voltage output from the precharger is coupled to a drain terminal of the TUT. In one example, the drain voltage output is coupled to the capacitor at a first capacitor terminal. In one example, the drain voltage output is inputted to the combinational logic and is inputted to an output divider, wherein the output divider outputs a modified relaxation oscillator waveform. In another example, the pulse generator may contain combinational logic that controls asynchronous set and reset pins of a flip flop, with the clock pin being tied to ground. The set and reset pins can control the output state of the flip flop, and thereby control the precharger and TUT.
In one example, the modified relaxation oscillator waveform is the relaxation oscillator waveform with its associated relaxation oscillator period modified. In one example, the combinational logic includes one or more of an AND gate, a NAND gate, an OR gate and/or a NOR gate coupled to each other in accordance to whether the TUT is a negative channel metal oxide semiconductor (NMOS) TUT or a positive channel metal oxide semiconductor (PMOS) TUT. In one example, the modified relaxation oscillator waveform is inputted to a counter, the counter to output a digital current measurement of the TUT. In one example, the transistor under test (TUT) comprises a plurality of transistors under test (TUTs). In one example, a select signal is used to select one of the plurality of transistors under test (TUTs) for current measurement.
Another aspect of the disclosure provides an apparatus for digital current measurement for monitoring an in-situ device, the apparatus including: means for charging or discharging a capacitor, wherein the capacitor is coupled to a transistor under test (TUT); means for changing an oscillation state when a capacitor voltage of the capacitor crosses a threshold and for turning OFF the TUT; means for discharging the capacitor using the TUT; means for commencing precharging the capacitor after detecting the capacitor reaches a transition voltage; means for commencing discharging the capacitor after a precharger time delay; means for sustaining a relaxation oscillator waveform, wherein the relaxation oscillator waveform is based on turning OFF and turning ON the TUT; and means for generating a digital representation of a TUT current, wherein the TUT current is associated with a relaxation oscillator period of the relaxation oscillator waveform.
Another aspect of the disclosure provides a computer-readable medium storing computer executable code, operable on a device including at least one processor and at least one memory coupled to the at least one processor, wherein the at least one processor is configured to implement digital current measurement for monitoring an in-situ device, the computer executable code including: instructions for causing a computer to charge or discharge a capacitor using a transistor under test (TUT); instructions for causing the computer to change an oscillation state when a capacitor voltage of the capacitor crosses a threshold and turning OFF the TUT; instructions for causing the computer to discharge the capacitor using the TUT; instructions for causing the computer to commence precharging the capacitor after detecting the capacitor reaches a transition voltage; instructions for causing the computer to commence discharging the capacitor after a precharger time delay; instructions for causing the computer to sustain a relaxation oscillator waveform, wherein the relaxation oscillator waveform is based on turning OFF and turning ON the TUT; and instructions for causing the computer to generate a digital representation of a TUT current, wherein the TUT current is associated with a relaxation oscillator period of the relaxation oscillator waveform.
These and other aspects of the invention will become more fully understood upon a review of the detailed description, which follows. Other aspects, features, and embodiments of the present invention will become apparent to those of ordinary skill in the art, upon reviewing the following description of specific, exemplary embodiments of the present invention in conjunction with the accompanying figures. While features of the present invention may be discussed relative to certain embodiments and figures below, all embodiments of the present invention can include one or more of the advantageous features discussed herein. In other words, while one or more embodiments may be discussed as having certain advantageous features, one or more of such features may also be used in accordance with the various embodiments of the invention discussed herein. In similar fashion, while exemplary embodiments may be discussed below as device, system, or method embodiments it should be understood that such exemplary embodiments can be implemented in various devices, systems, and methods.
The detailed description set forth below in connection with the appended drawings is intended as a description of various configurations and is not intended to represent the only configurations in which the concepts described herein may be practiced. The detailed description includes specific details for the purpose of providing a thorough understanding of various concepts. However, it will be apparent to those skilled in the art that these concepts may be practiced without these specific details. In some instances, well known structures and components are shown in block diagram form in order to avoid obscuring such concepts.
In the electronics industry, transistors are fundamental constituents of electronic circuitry. For example, an integrated circuit or semiconductor wafer for some useful application may include a plurality of transistors integrated in a monolithic semiconductor material, for example, silicon. In one aspect, economic viability of an integrated circuit or semiconductor wafer depends on efficient and repeatable transistor production techniques. Consequently, transistor production on semiconductor wafers should be monitored and controlled carefully to ensure reasonable production yield. In one aspect, production yield is the percentage of manufactured electronic devices which successfully achieve their performance requirements. Production yield may depend on the semiconductor manufacturing process used to produce the electronic devices. In general, a carefully controlled process, i.e., with minimal process variations, results in improved production yield.
In one example, transistor production on integrated circuits or semiconductor wafers may have undesirable process variations which degrade electronic device performance. Thus, certain transistor characteristics, such as transistor current, may need to be monitored to assess process variations on the wafers or integrated circuits. Current electronic designs may include special wafers which incorporate non-operational circuitry which measure transistor characteristics (e.g., transistor current) on the wafer. However, such special wafers cannot be sold since the non-operational circuitry prevents full functionality. Thus, this limitation drives a need for in-situ (i.e., on site) device monitoring. In one example, the present disclosure relates to a transistor measurement system for in-situ device monitoring for operational circuitry.
In one aspect, integrated circuit layout effects may alter transistor parameters such as threshold voltage or mobility which may result in a change in transistor current. Integrated circuit layout effects on a transistor may include short-range layout effects and long-range layout effects. For example, short-range layout effects may include features such as distance to active area, distance to polysilicon cut, distance between gate and active edge, distance from active edge to implant edge or well edge, etc. In one example, short-range layout effects in 10 nm technology may be related to layout geometries that are typically less than 1 micron (10−6 meter) distance from the transistor. In one example, 10 nm technology includes semiconductor devices with minimum feature sizes as low as 10 nm.
For example, long-range layout effects may include pattern density of transistor active area and polysilicon around the transistor of interest over a distance of a few microns and long-range gradients across a die or wafer over a distance of hundreds of microns up to a few centimeters (10−2 meter) in range.
In one example, the first flip flop output 316 is a relaxation oscillator waveform. The relaxation oscillator waveform includes a relaxation oscillator frequency or a relaxation oscillator period. The relaxation oscillator frequency is a reciprocal of the relaxation oscillator period. And, the relaxation oscillator period is a reciprocal of the relaxation oscillator frequency.
Next, the first flip flop output 316 is also connected to a gate voltage input (VGate) 321, a precharger 320 and a first TUT connection 331. The first TUT connection 331 is connected to a gate terminal of a transistor under test (TUT) 330. A drain voltage output (VDrain) 322 from the precharger 320 is connected to a second TUT connection 332. The second TUT connection 332 is connected to a drain terminal of the TUT 330. As shown in
In one example, the output divider 370 includes a third inverter 380, a second flip flop 390 and a fourth inverter 385. The second inverter output 362 connects to the third inverter input 381 (i.e., input of the third inverter 380). In one example, the third inverter input 381 is an input of the output divider 370. The third inverter 380 includes a third inverter output 382 which is connected to a second clock input 391of the second flip flop 390. In one aspect, the output divider 370 may lower an output frequency in half and may also reduce duty cycle distortion in an output waveform. In one example, the output waveform is the relaxation oscillator waveform which is modified by, for example, lowering its associated relaxation oscillator frequency. The relaxation oscillator frequency is the reciprocal of the relaxation oscillator period. The output (labeled as out 395) of the output divider 370 is a modified relaxation oscillator waveform.
In one example, there may be zero or more output divider stages. In one example, the third inverter 380 may reduce loading on the second inverter 360. In one example, the first flip flop 315 and the second flip flop 390 are asynchronous reset flip flops that are held in a reset state when the measurement tile is not enabled.
One skilled in the art would understand that the components listed herein for the example 300 of the measurement tile with a transistor under test (TUT) are examples and the types of components and/or its quantity may vary within the spirit and scope of the present disclosure. And, it is understood that other components (although not explicitly listed herein) may be included as part of the example 300 of the measurement tile with the transistor under test (TUT). One skilled in the art would also understand that the connections of the various components as shown in the example of
In one example, the first flip flop output 416 is a relaxation oscillator waveform. The relaxation oscillator waveform includes a relaxation oscillator frequency or a relaxation oscillator period. The relaxation oscillator frequency is a reciprocal of the relaxation oscillator period. And, the relaxation oscillator period is a reciprocal of the relaxation oscillator frequency.
In one example, the combinational logic 418 may include one or more of the following components: a NOR gate 403, a delay element 404, an internal inverter 405, a first NAND gate 406, a second NAND gate 407, a third NAND gate 408, and a clock 409. In the example of
One skilled in the art would understand that the components listed herein for the combinational logic 418 are examples and the types of components and/or its quantity may vary within the spirit and scope of the present disclosure. And, it is understood that other components (although not explicitly listed herein) may be included as part of the combinational logic 418. One skilled in the art would also understand that the connections of the various components of the combinational logic 418 as shown in the example of FIG. 4 is not an exclusive one. That is, other connections between the various components of the combinational logic 418 are also within the spirit and scope of the present disclosure.
In the example of
In the example of
In one example, there may be zero or more output divider stages. In one example, the third inverter 480 may reduce loading on the second inverter 460. In one example, the first flip flop 415 and the second flip flop 490 are asynchronous reset flip flops that are held in a reset state when the measurement tile is not enabled.
One skilled in the art would understand that the components listed herein for the example NMOS digital relaxation oscillator 400 are examples and the types of components and/or its quantity may vary within the spirit and scope of the present disclosure. And, it is understood that other components (although not explicitly listed herein) may be included as part of the example NMOS digital relaxation oscillator 400. One skilled in the art would also understand that the connections of the various components as shown in the example of
In one example, the first flip flop output 516 is a relaxation oscillator waveform. The relaxation oscillator waveform includes a relaxation oscillator frequency or a relaxation oscillator period. The relaxation oscillator frequency is a reciprocal of the relaxation oscillator period. And, the relaxation oscillator period is a reciprocal of the relaxation oscillator frequency.
In one example, combinational logic 518 may include one or more of the following components: an AND gate 503, a delay element 504, a first NAND gate 506, an OR gate 507, a second NAND gate 508, and a clock 509. In one example, the delay element 504 sets a precharger time delay by its delay characteristics. In the example of
As shown in
In the example of
In one example, there may be zero or more output divider stages. In one example, the third inverter 580 may reduce loading on the second inverter 560. In one example, the first flip flop 515 and the second flip flop 590 are asynchronous reset flip flops that are held in a reset state when the measurement tile is not enabled.
One skilled in the art would understand that the components listed herein for the example PMOS digital relaxation oscillator 500 are examples and the types of components and/or its quantity may vary within the spirit and scope of the present disclosure. And, it is understood that other components (although not explicitly listed herein) may be included as part of the example PMOS digital relaxation oscillator 500. One skilled in the art would also understand that the connections of the various components as shown in the example of
One skilled in the art would understand that the components for the example 600 are examples and the types of components and/or its quantity may vary within the spirit and scope of the present disclosure. And, it is understood that other components (although not explicitly listed herein) may be included as part of the example 600. One skilled in the art would also understand that the connections of the various components as shown in the example of
In one example, a first TUT connection 731 is connected to a gate voltage input (VGate) at a precharger 720. The first TUT connection 731 provides an enable signal (Venable) 785. As shown in
In one example, an output of the first AND gate 781 is connected to a gate terminal (labeled as GT) of first NMOS TUT 791. In one example, an output of the second AND gate 782 is connected to a gate terminal (labeled as GT) of second NMOS TUT 792. In one example, an output of the third AND gate 783 is connected to a gate terminal (labeled as GT) of third NMOS TUT 793. In one example, an output of the fourth AND gate 784 is connected to a gate terminal (labeled as GT) of fourth NMOS TUT 794.
In example 700, a drain voltage output (VDrain) 722 from the predischarger 720 is connected to a second TUT connection 732. As shown in
In one example, if the enable signal (Venable) 785 is in a HIGH state, then selection of one of the plurality of NMOS TUTs (i.e., 791, 792, 793, 794) for digital current measurement may be made by assertion of one of a plurality of select signals: first select signal (Select0) 786, second select signal (Select1) 787, third select signal (Select2) 788, third select signal (Select3) 789. For example, assertion of Select0786 selects first NMOS TUT 791, assertion of Select1787 selects second NMOS TUT 792, assertion of Select2788 selects third NMOS TUT 793, and assertion of Select3789 selects fourth NMOS TUT 794. In one example, assertion of a select signal means setting the select signal to a HIGH state.
One skilled in the art would understand that the components for the example 700 are examples and the types of components and/or its quantity may vary within the spirit and scope of the present disclosure. And, it is understood that other components (although not explicitly listed herein) may be included as part of the example 700. One skilled in the art would also understand that the connections of the various components as shown in the example of
In one example, a first TUT connection 831 is connected to a gate voltage input (VGate) at a precharger 820. The first TUT connection 831 provides an enable signal (Venable) 885. In one example, if the enable signal (Venable) 885 is in a HIGH state, then selection of one of the plurality of multiplexers (e.g., mux1871, mux2872, mux3873, and mux4874) for control of analog voltage level to the gate terminals (labeled as GT) of the plurality of NMOS TUTs 891, 892, 893, 894 may be made by assertion of one of a plurality of select signals: Select0886, Select1887, Select2888, Select3889. For example, assertion of Select0886 selects analog voltage level VLDO to a gate terminal (labeled as GT) of first NMOS TUT 891, assertion of Select1887 selects analog voltage level VLDO to a gate terminal (labeled as GT) of second NMOS TUT 892, assertion of Select2888 selects analog voltage level VLDO to a gate terminal (labeled as GT) of third NMOS TUT 893, and assertion of Select3889 selects analog voltage level VLDO to a gate terminal (labeled as GT) of fourth NMOS TUT 894. In one example, assertion of a select signal means setting the select signal to a HIGH state. Similar to
In one example, a design goal is a measurement circuit which can measure a transistor under test (TUT) current and produce a digital measurement of the TUT current. In one example, the measurement circuit is compatible with a standard cell integrated circuit environment. For example, there may be an even number of standard cell rows and the design may be in a standard cell style. For example, the measurement circuit may be small and easy to integrate to allow placement throughout a standard cell design and may be designed to attach onto a transistor under test (TUT) tile. In one example, a minimum number of patterns on a die is approximately 10,000. One skilled in the art would understand that the number of patterns at approximately 10,000 is only an example and that other minimum numbers of the patterns not mentioned herein may also be within the spirit and scope of the present disclosure.
Disclosed herein in one aspect is an in-situ digital measurement circuit which converts a transistor under test (TUT) current or inverse current to a relaxation oscillator parameter. For example, the TUT current is denoted as I and the TUT inverse current is denoted as I−1, where 1/I=I−1. In one example, the relaxation oscillator parameter may be either a relaxation oscillator frequency Fosc or a relaxation oscillator period Tosc. In one example, the relaxation oscillator frequency Fosc is the reciprocal of the relaxation oscillator period Tosc, that is, Fosc=1/Tosc. In one example, the relaxation oscillator frequency Fosc or the relaxation oscillator period Tosc is a function of the transistor under test current I or inverse current I−1. A counter circuit may be used to measure the relaxation oscillator frequency Fosc, or its period Tosc, to produce a digital representation of the transistor under test current I or inverse current I−1. More specifically, the counter circuit measures the relaxation oscillator period Tosc which is linearly related to the transistor under test inverse current I−1. Thus, the counter circuit output may be used to determine the TUT current. With this in-situ digital measurement circuit, transistor current may be tracked throughout the device life cycle to monitor performance variation over process, voltage and temperature (PVT).
In one example, an all-digital measurement tile on an integrated circuit or semiconductor wafer is used which places a TUT within a relaxation oscillator circuit where the relaxation oscillator frequency Fosc or the relaxation oscillator period Tosc depends on the TUT current I or TUT inverse current I−1. In one example, the TUT may be a negative metal oxide semiconductor (NMOS) transistor or a positive metal oxide semiconductor (PMOS). In one aspect, an NMOS measurement tile is used to monitor NMOS transistors and a PMOS measurement tile is used to monitor PMOS transistors. The elements of the measurement tile may include the TUT, a pre-charger and a capacitor arranged in a feedback loop to operate as an oscillator as the capacitor charges and discharges. The pre-charger time constant may be determined by a precharger time delay to facilitate measurement calibration.
In one example, a conversion equation relates quantitatively the relaxation oscillator period Tosc to the TUT current I or TUT inverse current I−1. In one example, the conversion equation has the form of a linear equation of relaxation oscillator period Tosc vs. TUT inverse current I−1:
T
osc
=C ΔV I
−1
+t
ckt
where Tosc=relaxation oscillator period=1/oscillator frequency (Fosc),
and tckt=circuit offset time due to the precharger time delay.
In one example, C is a capacitance value of the capacitor and ΔV is the change of voltage of the capacitor, and C ΔV is the slope of the linear equation. In one example, the relaxation oscillator period Tosc is a characteristic of a relaxation oscillator waveform, wherein the relaxation oscillator waveform is based on turning OFF and turning ON of the TUT.
In one example, since the conversion equation includes a slope C ΔV and the current offset time tckt which are process dependent, a calibration process may be needed to minimize the transistor current measurement error. In one example, the calibration process may require two known currents to fit the linear equation of the relaxation oscillator period Tosc vs. TUT inverse current I−1 to an absolute current value. In one example, process dependent means that a manufacturing technique used to produce the TUT may affect the slope C ΔV and the current offset time tckt.
For example, the calibration process may use a current mirror replication of a reference current to provide two known currents. In a first calibration method, current of reference transistors may be determined by physical measurement of current of test structure transistors which have identical layout to the reference transistors. In one example, the reference transistors may have previously determined currents, or known currents. In one example, the quantity of reference transistors is two.
In a second calibration method, a circuit simulation model of the reference transistors using a circuit simulation tool may be used to extract circuit parameters for the reference transistors using identical transistors configured as a ring oscillator. An example of a circuit simulation tool is SPICE. SPICE is known as Simulation Program with Integrated Circuit Emphasis and is a general-purpose, open source analog electronic circuit simulator which is used in integrated circuit design to check the integrity of the integrated circuit designs.
For example, if the ring oscillator frequency or period is measured at a plurality of supply voltages and compared to the circuit simulation model, sensitivity to the circuit simulation tool parameters may be determined to obtain a sensitivity matrix [S] and another circuit simulation model of the reference transistors may be generated. Next, the circuit simulation model may be used to create a linear system of equations of the form, for example:
[S][H]=[F], where
[H]=circuit simulation model vector,
[S]=sensitivity matrix, and
[F]=ring oscillator frequency vector.
In one example, the linear system of equations may be solved either analytically or via simulation techniques.
In one example, the measurement circuit measures average transistor current as the drain voltage varies from maximum drain voltage VDD to half maximum drain voltage VDD/2 (e.g., for NMOS transistors) and as the gate voltage varies from VDD to VDD/2. For example, there are two strategies for the measurement circuit. A first strategy may be placing measurement tiles around a circuit die under test to sample local layout variations around the circuit die under test. A second strategy may be placing measurement tiles in a layout pattern without consideration of a local layout environment. In one example, the second strategy may cluster measurement tiles in low utilization areas.
In one example, a test time Ttest for the measurement circuit depends on a sum of measurement time Tmeas and a scan time Tscan. The measurement time Tmeas depends on a product of a reference clock period Tref, a number of reference clock periods Nref per TUT measurement, and a total number of TUTs being measured NT. The scan time Tscan depends on a product of a scan clock period Ts, a number of scans Ns, and the total number of TUTs being measured NT. For example, the test time Ttest may be expressed as:
T
test
=T
meas.
+T
scan
T
test
=T
ref
N
ref
N
T.
+T
s
N
s
N
T.
In one example, if the reference clock period Tref is 25 ns (i.e., reciprocal of 40 MHz), the number of reference clock periods Nref is 500, the scan clock period Ts is 20 ns (i.e., reciprocal of 50 MHz), the number of scans Ns is 512, the total number of TUTs being measured NT is 10,000, then the test time Ttest is:
T
test=(25 ns) (500)(10,000)+(20 ns) (512) (10,000)
T
test=125 ms+102.4 ms=227.4 ms.
In one example, the test time Ttest is proportional to the total number of TUTs being measured NT.
In block 1120, change an oscillation state when a capacitor voltage of the capacitor crosses a threshold and turns OFF the TUT. In one example, the threshold is predetermined based on one or more characteristics of the TUT. In one example, the threshold is half of a maximum value of the drain voltage of the TUT. In one example, a pulse generator turns OFF the TUT. In one example, changing the oscillation state is to change from one voltage level to another voltage level. In one example, the threshold is determined by the switching point of an inverter connected to the capacitor. The inverter may act as a comparator and may change its state when the capacitor voltage is approximately at half the drain voltage of the TUT. In one example, the drain voltage is also known as the supply voltage of the TUT.
In block 1130, discharge the capacitor using the TUT.
In block 1140, commence precharging the capacitor after detecting the capacitor reaches a transition voltage. In one example, the transition voltage is a half maximum value of the drain voltage of the TUT. In one example, the detecting is performed by the inverter. In one example, the precharging is performed by the pulse generator.
In block 1150, commence discharging the capacitor after a precharger time delay. In one example, the precharger time delay is chosen to ensure an adequate precharge time and to ensure that the precharge time is independent of precharger strength and variation. In one example, the precharge for an NMOS sensor is made from several PMOS transistors. The more PMOS transistors that are used, the faster the capacitor will precharge because there are more transistors providing current. Similarly, if the PMOS transistors use a lower threshold voltage, a shorter channel length, or a larger width, more total current will be available to precharge the capacitor, and the capacitor will precharge faster. That is, the precharger strength refers to the amount of current the precharger provides. In one example, the precharger strength may depend on transistor length, width, threshold voltage and quantity. The strength of the precharger refers to the amount of current it can provide, and therefore refers to width, length, threshold voltage, and number of transistors. In another example, variation may refer to normal manufacturing variation which results in differences in transistor length, width and threshold voltage for nominally identical transistors.
In block 1160, sustain a relaxation oscillator waveform, wherein the relaxation oscillator waveform is based on turning OFF and turning ON the TUT. In one example the relaxation oscillator waveform includes a relaxation oscillator period which is a reciprocal of a relaxation oscillator frequency. In one example, the pulse generator sustains the relaxation oscillator waveform by an inverting feedback loop and an ON/OFF state of the TUT. The ON/OFF state is an indication of whether the TUT is turned ON or turned OFF. In one example, the inverting feedback loop includes a flip flop coupled to an inverter (e.g., a first flip flop 315 and a first inverter 312 as shown in
In block 1170, generate a digital representation of a TUT current, wherein the TUT current is associated with a relaxation oscillator period of the relaxation oscillator waveform. In one example, a counter is used to generate the digital representation of the TUT current. In one example, a conversion equation is used to convert the relaxation oscillator period to an inverse current of the TUT. The inverse current is a reciprocal of the TUT current. In one example, the conversion equation is as follows:
T
osc
=C ΔV I
−1
+t
ckt
where Tosc=relaxation oscillator period=1/oscillator frequency (Fosc),
and tckt=circuit offset time due to a precharger time delay.
In one example, the digital current measurement (as disclosed in
In one aspect, one or more of the steps for providing digital current measurement for in-situ device monitoring in
The computer-readable medium may also include, by way of example, a carrier wave, a transmission line, and any other suitable medium for transmitting software and/or instructions that may be accessed and read by a computer. The computer-readable medium may reside in the processing system, external to the processing system, or distributed across multiple entities including the processing system. The computer-readable medium may be embodied in a computer program product. By way of example, a computer program product may include a computer-readable medium in packaging materials. The computer-readable medium may include software or firmware for digital current measurement for in-situ device monitoring. Those skilled in the art will recognize how best to implement the described functionality presented throughout this disclosure depending on the particular application and the overall design constraints imposed on the overall system.
Any circuitry included in the processor(s) is merely provided as an example, and other means for carrying out the described functions may be included within various aspects of the present disclosure, including but not limited to the instructions stored in the computer-readable medium, or any other suitable apparatus or means described herein, and utilizing, for example, the processes and/or algorithms described herein in relation to the example flow diagram.
Within the present disclosure, the word “exemplary” is used to mean “serving as an example, instance, or illustration.” Any implementation or aspect described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other aspects of the disclosure. Likewise, the term “aspects” does not require that all aspects of the disclosure include the discussed feature, advantage or mode of operation. The term “coupled” is used herein to refer to the direct or indirect coupling between two objects. For example, if object A physically touches object B, and object B touches object C, then objects A and C may still be considered coupled to one another—even if they do not directly physically touch each other. For instance, a first die may be coupled to a second die in a package even though the first die is never directly physically in contact with the second die. The terms “circuit” and “circuitry” are used broadly, and intended to include both hardware implementations of electrical devices and conductors that, when connected and configured, enable the performance of the functions described in the present disclosure, without limitation as to the type of electronic circuits, as well as software implementations of information and instructions that, when executed by a processor, enable the performance of the functions described in the present disclosure.
One or more of the components, steps, features and/or functions illustrated in the figures may be rearranged and/or combined into a single component, step, feature or function or embodied in several components, steps, or functions. Additional elements, components, steps, and/or functions may also be added without departing from novel features disclosed herein. The apparatus, devices, and/or components illustrated in the figures may be configured to perform one or more of the methods, features, or steps described herein. The novel algorithms described herein may also be efficiently implemented in software and/or embedded in hardware.
It is to be understood that the specific order or hierarchy of steps in the methods disclosed is an illustration of exemplary processes. Based upon design preferences, it is understood that the specific order or hierarchy of steps in the methods may be rearranged. The accompanying method claims present elements of the various steps in a sample order, and are not meant to be limited to the specific order or hierarchy presented unless specifically recited therein.
The previous description is provided to enable any person skilled in the art to practice the various aspects described herein. Various modifications to these aspects will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other aspects. Thus, the claims are not intended to be limited to the aspects shown herein, but are to be accorded the full scope consistent with the language of the claims, wherein reference to an element in the singular is not intended to mean “one and only one” unless specifically so stated, but rather “one or more.” Unless specifically stated otherwise, the term “some” refers to one or more. A phrase referring to “at least one of” a list of items refers to any combination of those items, including single members. As an example, “at least one of: a, b, or c” is intended to cover: a; b; c; a and b; a and c; b and c; and a, b and c. All structural and functional equivalents to the elements of the various aspects described throughout this disclosure that are known or later come to be known to those of ordinary skill in the art are expressly incorporated herein by reference and are intended to be encompassed by the claims. Moreover, nothing disclosed herein is intended to be dedicated to the public regardless of whether such disclosure is explicitly recited in the claims. No claim element is to be construed under the provisions of 35 U.S.C. § 112, sixth paragraph, unless the element is expressly recited using the phrase “means for” or, in the case of a method claim, the element is recited using the phrase “step for.”
