Myongseob Kim

Person

Pleasanton, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Integrated circuit (IC) structure protection scheme
- Patent number 12,068,257
- Issue date Aug 20, 2024
- Xilinx, Inc.
- Myongseob Kim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Interwafer connection structure for coupling wafers in a wafer stack
- Patent number 11,901,338
- Issue date Feb 13, 2024
- Xilinx, Inc.
- Myongseob Kim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Stacked silicon package assembly having thermal management
- Patent number 11,355,412
- Issue date Jun 7, 2022
- Xilinx, Inc.
- Jaspreet Singh Gandhi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit device with stacked dies having mirrored circuitry
- Patent number 11,205,639
- Issue date Dec 21, 2021
- Xilinx, Inc.
- Myongseob Kim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multi-die device structures and methods
- Patent number 11,114,360
- Issue date Sep 7, 2021
- Xilinx, Inc.
- Jaspreet Singh Gandhi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
IC die with dummy structures
- Patent number 11,114,344
- Issue date Sep 7, 2021
- Xilinx, Inc.
- Hui-Wen Lin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Test circuits for testing a die stack
- Patent number 11,054,461
- Issue date Jul 6, 2021
- Xilinx, Inc.
- Nui Chong
- G01 - MEASURING TESTING
Information Patent Grant
Package integration for memory devices
- Patent number 10,770,430
- Issue date Sep 8, 2020
- Xilinx, Inc.
- Myongseob Kim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Chip package assembly with modular core dice
- Patent number 10,692,837
- Issue date Jun 23, 2020
- Xilinx, Inc.
- Myongseob Kim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods and apparatus for thermal interface material (TIM) bond lin...
- Patent number 10,529,645
- Issue date Jan 7, 2020
- Xilinx, Inc.
- Jaspreet Singh Gandhi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Wafer edge partial die engineered for stacked die yield
- Patent number 10,431,565
- Issue date Oct 1, 2019
- Xilinx, Inc.
- Myongseob Kim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Circuit for and method of testing bond connections between a first...
- Patent number 10,262,911
- Issue date Apr 16, 2019
- Xilinx, Inc.
- Yuqing Gong
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Shielded wire arrangement for die testing
- Patent number 9,412,674
- Issue date Aug 9, 2016
- Xilinx, Inc.
- Myongseob Kim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and apparatus for tracking interposer dies in a silicon stac...
- Patent number 9,236,367
- Issue date Jan 12, 2016
- Xilinx, Inc.
- Cinti X. Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and apparatus for tracking interposer dies in a silicon stac...
- Patent number 8,987,009
- Issue date Mar 24, 2015
- Xilinx, Inc.
- Cinti X. Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of testing a semiconductor structure
- Patent number 8,810,269
- Issue date Aug 19, 2014
- Xilinx, Inc.
- Yuqing Gong
- G01 - MEASURING TESTING
Information Patent Grant
Methods of manufacturing a semiconductor structure
- Patent number 8,802,454
- Issue date Aug 12, 2014
- Xilinx, Inc.
- Arifur Rahman
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Memory structure having SRAM cells and SONOS devices
- Patent number 8,542,514
- Issue date Sep 24, 2013
- Cypress Semiconductor Corporation
- Sethuraman Lakshminarayanan
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor device and method for making the same
- Patent number 8,329,568
- Issue date Dec 11, 2012
- Xilinx, Inc.
- Jae-Gyung Ahn
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Transistor with floating gate and electret
- Patent number 7,960,776
- Issue date Jun 14, 2011
- Cornell Research Foundation, Inc.
- Myongseob Kim
- G01 - MEASURING TESTING

Patents Applicationslast 30 patents

Information Patent Application
CHIP PACKAGE ASSEMBLY WITH ENHANCED SOLDER PITCH
- Publication number 20240321793
- Publication date Sep 26, 2024
- Xilinx, Inc.
- Yun WU
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT (IC) Protections
- Publication number 20240145411
- Publication date May 2, 2024
- Xilinx, Inc.
- Myongseob KIM
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD FOR MITIGATING WARPAGE ON STACKED WAFERS
- Publication number 20240038556
- Publication date Feb 1, 2024
- Xilinx, Inc.
- Myongseob KIM
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTERWAFER CONNECTION STRUCTURE FOR COUPLING WAFERS IN A WAFER STACK
- Publication number 20230140675
- Publication date May 4, 2023
- Xilinx, Inc.
- Myongseob KIM
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT DEVICE WITH STACKED DIES HAVING MIRRORED CIRCUITRY
- Publication number 20210265312
- Publication date Aug 26, 2021
- Xilinx, Inc.
- Myongseob KIM
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PACKAGE INTEGRATION FOR MEMORY DEVICES
- Publication number 20200303341
- Publication date Sep 24, 2020
- Xilinx, Inc.
- Myongseob Kim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STACKED SILICON PACKAGE ASSEMBLY HAVING THERMAL MANAGEMENT
- Publication number 20200105642
- Publication date Apr 2, 2020
- Xilinx, Inc.
- Jaspreet Singh Gandhi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS AND APPARATUS FOR THERMAL INTERFACE MATERIAL (TIM) BOND LIN...
- Publication number 20180358280
- Publication date Dec 13, 2018
- Xilinx, Inc.
- Jaspreet Singh Gandhi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD OF TESTING A SEMICONDUCTOR STRUCTURE
- Publication number 20140091819
- Publication date Apr 3, 2014
- Xilinx, Inc.
- Yuqing Gong
- G01 - MEASURING TESTING
Information Patent Application
TRANSISTOR WITH FLOATING GATE AND ELECTRET
- Publication number 20080094074
- Publication date Apr 24, 2008
- Myongseob Kim
- G01 - MEASURING TESTING

Myongseob Kim

Person

Patents Grantslast 30 patents

Integrated circuit (IC) structure protection scheme

Interwafer connection structure for coupling wafers in a wafer stack

Stacked silicon package assembly having thermal management

Integrated circuit device with stacked dies having mirrored circuitry

Multi-die device structures and methods

IC die with dummy structures

Test circuits for testing a die stack

Package integration for memory devices

Chip package assembly with modular core dice

Methods and apparatus for thermal interface material (TIM) bond lin...

Wafer edge partial die engineered for stacked die yield

Circuit for and method of testing bond connections between a first...

Shielded wire arrangement for die testing

Method and apparatus for tracking interposer dies in a silicon stac...

Method and apparatus for tracking interposer dies in a silicon stac...

Method of testing a semiconductor structure

Methods of manufacturing a semiconductor structure

Memory structure having SRAM cells and SONOS devices

Semiconductor device and method for making the same

Transistor with floating gate and electret

Patents Applicationslast 30 patents

CHIP PACKAGE ASSEMBLY WITH ENHANCED SOLDER PITCH

INTEGRATED CIRCUIT (IC) Protections

METHOD FOR MITIGATING WARPAGE ON STACKED WAFERS

INTERWAFER CONNECTION STRUCTURE FOR COUPLING WAFERS IN A WAFER STACK

INTEGRATED CIRCUIT DEVICE WITH STACKED DIES HAVING MIRRORED CIRCUITRY

PACKAGE INTEGRATION FOR MEMORY DEVICES

STACKED SILICON PACKAGE ASSEMBLY HAVING THERMAL MANAGEMENT

METHODS AND APPARATUS FOR THERMAL INTERFACE MATERIAL (TIM) BOND LIN...

METHOD OF TESTING A SEMICONDUCTOR STRUCTURE

TRANSISTOR WITH FLOATING GATE AND ELECTRET