Myung Chan Choi

Person

San Jose, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Latency control circuit and method
- Patent number 11,004,499
- Issue date May 11, 2021
- Winbond Electronics Corp.
- Young-Tae Kim
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory device and power reduction method of the same memory device
- Patent number 10,564,692
- Issue date Feb 18, 2020
- Windbond Electronics Corp.
- Myung-Chan Choi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Delay locked loop circuit and method of controlling same
- Patent number 10,217,497
- Issue date Feb 26, 2019
- Winbond Electronics Corporation
- Myung Chan Choi
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory device having input circuit and operating method of same
- Patent number 9,721,675
- Issue date Aug 1, 2017
- Winbond Electronics Corporation
- Myung Chan Choi
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory with specific driving mechanism applied on source line
- Patent number 9,263,127
- Issue date Feb 16, 2016
- Winbond Electronics Corp.
- Myung Chan (Mickey) Choi
- G11 - INFORMATION STORAGE
Information Patent Grant
Burst sequence control and multi-valued fuse scheme in memory device
- Patent number 9,202,532
- Issue date Dec 1, 2015
- Winbond Electronics Corp.
- Myung Chan Choi
- G11 - INFORMATION STORAGE
Information Patent Grant
Low power memory control circuits and methods
- Patent number 7,929,367
- Issue date Apr 19, 2011
- ZMOS Technology, Inc.
- Seung-Moon Yoo
- G11 - INFORMATION STORAGE
Information Patent Grant
Low voltage operation DRAM control circuits
- Patent number 7,839,701
- Issue date Nov 23, 2010
- ZMOS Technology, Inc.
- Myung Chan Choi
- G11 - INFORMATION STORAGE
Information Patent Grant
Source transistor configurations and control methods
- Patent number 7,705,625
- Issue date Apr 27, 2010
- ZMOS Technology, Inc.
- Seung-Moon Yoo
- G11 - INFORMATION STORAGE
Information Patent Grant
Dynamic memory refresh configurations and leakage control methods
- Patent number 7,522,464
- Issue date Apr 21, 2009
- ZMOS Technology, Inc.
- Seung-Moon Yoo
- G11 - INFORMATION STORAGE
Information Patent Grant
Low voltage operation dram control circuits
- Patent number 7,324,390
- Issue date Jan 29, 2008
- ZMOS Technology, Inc.
- Myung Chan Choi
- G11 - INFORMATION STORAGE
Information Patent Grant
CMOS constant voltage generator
- Patent number 7,301,322
- Issue date Nov 27, 2007
- ZMOS Technology, Inc.
- Myung Chan Choi
- G05 - CONTROLLING REGULATING
Information Patent Grant
Low voltage operation DRAM control circuits
- Patent number 7,082,048
- Issue date Jul 25, 2006
- Zmos Technology, Inc.
- Myung Chan Choi
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
MEMORY DEVICE AND POWER REDUCTION METHOD OF THE SAME MEMORY DEVICE
- Publication number 20190304530
- Publication date Oct 3, 2019
- WINBOND ELECTRONICS CORP.
- Myung-Chan Choi
- G11 - INFORMATION STORAGE
Information Patent Application
DELAY LOCKED LOOP CIRCUIT AND METHOD OF CONTROLLING SAME
- Publication number 20180358061
- Publication date Dec 13, 2018
- Winbond Electronics Corporation
- Myung Chan CHOI
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Memory with specific driving mechanism applied on source line
- Publication number 20160049196
- Publication date Feb 18, 2016
- WINBOND ELECTRONICS CORP.
- Myung Chan (Mickey) CHOI
- G11 - INFORMATION STORAGE
Information Patent Application
Burst Sequence Control And Multi-Valued Fuse Scheme In Memory Device
- Publication number 20140071770
- Publication date Mar 13, 2014
- WINBOND ELECTRONICS CORP.
- Myung Chan Choi
- G11 - INFORMATION STORAGE
Information Patent Application
LOW POWER MEMORY CONTROL CIRCUITS AND METHODS
- Publication number 20120201085
- Publication date Aug 9, 2012
- ZMOS TECHNOLOGY, INC.
- Seung-Moon Yoo
- G11 - INFORMATION STORAGE
Information Patent Application
DYNAMIC MEMORY REFRESH CONFIGURATIONS AND LEAKAGE CONTROL METHODS
- Publication number 20080031068
- Publication date Feb 7, 2008
- ZMOS TECHNOLOGY, INC.
- Seung-Moon Yoo
- G11 - INFORMATION STORAGE
Information Patent Application
LOW VOLTAGE OPERATION DRAM CONTROL CIRCUITS
- Publication number 20080008018
- Publication date Jan 10, 2008
- ZMOS TECHNOLOGY, INC.
- Myung Chan Choi
- G11 - INFORMATION STORAGE
Information Patent Application
LOW POWER MEMORY CONTROL CIRCUITS AND METHODS
- Publication number 20070081405
- Publication date Apr 12, 2007
- ZMOS TECHNOLOGY, INC.
- Seung-Moon Yoo
- G11 - INFORMATION STORAGE
Information Patent Application
Source transistor configurations and control methods
- Publication number 20070063763
- Publication date Mar 22, 2007
- Seung-Moon Yoo
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Low voltage operation dram control circuits
- Publication number 20060227593
- Publication date Oct 12, 2006
- Myung Chan Choi
- G11 - INFORMATION STORAGE
Information Patent Application
Internal voltage generator scheme and power management method
- Publication number 20050259497
- Publication date Nov 24, 2005
- ZMOS TECHNOLOGY, INC.
- Myung Chan Choi
- G05 - CONTROLLING REGULATING
Information Patent Application
CMOS constant voltage generator
- Publication number 20050184797
- Publication date Aug 25, 2005
- Myung Chan Choi
- G05 - CONTROLLING REGULATING
Information Patent Application
Low voltage operation DRAM control circuits
- Publication number 20050083769
- Publication date Apr 21, 2005
- ZMOS TECHNOLOGY, INC.
- Myung Chan Choi
- G11 - INFORMATION STORAGE

Myung Chan Choi

Person

Patents Grantslast 30 patents

Latency control circuit and method

Memory device and power reduction method of the same memory device

Delay locked loop circuit and method of controlling same

Memory device having input circuit and operating method of same

Memory with specific driving mechanism applied on source line

Burst sequence control and multi-valued fuse scheme in memory device

Low power memory control circuits and methods

Low voltage operation DRAM control circuits

Source transistor configurations and control methods

Dynamic memory refresh configurations and leakage control methods

Low voltage operation dram control circuits

CMOS constant voltage generator

Low voltage operation DRAM control circuits

Patents Applicationslast 30 patents

MEMORY DEVICE AND POWER REDUCTION METHOD OF THE SAME MEMORY DEVICE

DELAY LOCKED LOOP CIRCUIT AND METHOD OF CONTROLLING SAME

Memory with specific driving mechanism applied on source line

Burst Sequence Control And Multi-Valued Fuse Scheme In Memory Device

LOW POWER MEMORY CONTROL CIRCUITS AND METHODS

DYNAMIC MEMORY REFRESH CONFIGURATIONS AND LEAKAGE CONTROL METHODS

LOW VOLTAGE OPERATION DRAM CONTROL CIRCUITS

LOW POWER MEMORY CONTROL CIRCUITS AND METHODS

Source transistor configurations and control methods

Low voltage operation dram control circuits

Internal voltage generator scheme and power management method

CMOS constant voltage generator

Low voltage operation DRAM control circuits