Patent Application
20070081405
Not Applicable
Not Applicable
A portion of the material in this patent document is subject to copyright protection under the copyright laws of the United States and of other countries.
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1. Field of the Invention
This invention pertains generally to memory devices, and more particularly to control circuits within memory devices.
2. Description of Related Art
Memory devices as well as many other electronic circuits incorporate memory cells within which are retained bits of digital data. These memory cells can be static or dynamic in nature. In dynamic random access memory (DRAM) the memory cells are so volatile that a charge restoring operation is needed to maintain cell information. This charge-restoration operation is referred to as a refresh operation, such as performed by a memory controller. Depletion of the charge from the memory cell arises through several leakage sources. A major portion of the leakage arises from a sub-threshold leakage current which constitutes a major portion of the total leakage current. In a conventional DRAM cell organization which shares a bitline among many memory cells, the shortest data retention time arises during memory block activation.
Accordingly, a need exists for circuits and methods for reducing leakage current within memory circuits, and in particular dynamic memory circuits. These needs and others are met within the present invention, which overcomes the deficiencies of previously developed circuits and methods.
A number of circuits and methods are taught for reducing power consumption within memory circuits, and in particular dynamic memory circuits. A dynamic memory circuit includes a first cross-coupled transistor pair for sensing and amplifying a differential voltage between a first and second circuit nodes, herein referred to as LA and LAb. In response to sensing the differential voltage either said first or second circuit node is driven to a first voltage. The node to which this arises is the circuit node which is closest in voltage to the first voltage.
The invention is amenable to being embodied in a number of ways, including but not limited to the following descriptions.
An embodiment of the invention can be generally described as a circuit device, comprising: (a) a memory cell; (b) at least one memory access transistor coupled to the memory; and (c) wherein the memory access transistor is configured with a gate-to-source potential that changes in response to the operating mode of the circuit device.
The circuit and method of reducing power consumption is particularly well suited for dynamic random access memory (DRAM) in which memory state is maintained within a plurality of DRAM memory cells in response to performing refresh operations.
Within the circuit, the gate-to-source potential of the memory cell comprises a source potential which is higher than the gate potential, for example, the source potential can be higher than zero volts, or the gate potential lower than zero volts, or the source potential can be higher than zero volts and the gate potential also lower than zero volts.
In one implementation, a circuit is configured for changing the gate-to-source potential in response to reading the state of data within the memory cell.
By way of example, the circuit can comprise a bitline sense amplifier configured for controlling the source transistors. The circuit may comprise a latch device (i.e., CMOS) and a source transistor, which can be a power source transistor, ground source transistor, or a combination of source and ground transistors.
The present aspects of the invention can be implemented using different forms of source transistors. By way of example, a PMOS transistor can be used as a ground source transistor which changes the gate-to-source potential in response to reading the state of data within the memory cell. In one embodiment, the source of the PMOS transistor is coupled to the common node of two NMOS transistors of a CMOS latch, and the drain of the PMOS transistor is connected to ground. In this example, the gate potential of the PMOS transistor changes in response to operating mode of the memory device. The gate potential of the PMOS transistor is preferably controlled in response to receiving a pulsed signal, although other drive signals can be utilized.
The source transistors can be modulated in response to memory operating mode. For example, for a dynamic memory cell is configured so that the gate potential of the PMOS transistor is lower than zero volts in normal operating mode, and the gate potential is zero volts when the device is in refresh mode. The refresh mode can be controlled by a memory controller or memory device, or similar circuit.
Source transistors can comprise various arrangements of NMOS and PMOS transistors. In one example, an NMOS source transistor can be used as a ground source transistor which changes the gate-to-source potential in response to reading the state of data within the memory cell. In one implementation the drain of the NMOS source transistor is coupled to a common node of two NMOS transistors of a CMOS latch, and the source of the NMOS source transistor is connected to ground. In this case the NMOS source transistor gate potential changes in response to the operating mode of the circuit device. The gate potential of this NMOS source transistor is preferably controlled by a pulse signal, or by a reference voltage through an error detector, or other circuit which is responsive to device state.
An embodiment of the invention describes a dynamic memory (DRAM) device with improved memory retention, comprising: (a) a plurality of memory cells; (b) a pair of bitlines coupled to the memory cells; (c) wherein the memory cells are configured to maintain memory state in response to performing refresh operations; and (d) wherein the memory cells are configured with a cell data high potential which is boosted in self-refresh, or system controlled, refresh mode.
In one implementation, the equalized bitline level is higher in self-refresh mode than in normal operating mode, such as by being controlled by a bitline precharge level generator. The boosted potential of the bitline level can be controlled by a reference voltage signal through an error detector, a pulse signal, a combination of existing signals, or a combination of reference voltage signal, pulse signal, and mode entry and/or exit signals. Cell data high potential can be generated by using source transistors, such as comprising at least a first, second and third source transistor. For example, the first source transistor comprising a PMOS source transistor, and the second and third source transistors comprising NMOS source transistors.
In one example, the first transistor is configured for speeding up supply power, and is preferably connected to a power supply with a higher voltage potential than the supply voltage of second and third source transistors. The second source transistor in this example generates main power and the third source transistor generates auxiliary power. The source of first PMOS source transistor and the drain of first NMOS source transistor are preferably connected to internally generated power, and the drain of the second NMOS source transistor is connected to externally supplied power. The gate of the second NMOS source transistor can be controlled by a pulse or a combination of pulse and mode entry and/or exit signals. The second NMOS source transistor is configured to provide a turn-on time in self-refresh mode that exceeds the turn-on time in normal operating mode.
An embodiment of the invention describes a dynamic memory (DRAM) device, comprising: (a) a plurality of memory cells; (b) wherein memory state of the dynamic memory is maintained in response to performing refresh operations; (c) a pair of bitlines coupled to the memory cells; (d) a bitline sense amplifier coupled to the bitlines for sensing the state of memory cells; (e) a plurality of source transistors coupled to the bitline sense amplifier; (f) the plurality of source transistors preferably comprises a first PMOS source transistor, a first second NMOS source transistor; wherein the source transistors are connected to a latch within the bitline sense amplifier.
According to one implementation, the source of the first PMOS source transistor, and the drain of the first NMOS source transistor, are connected to internally generated power, and the drain of the second NMOS source transistor is connected to externally supplied power. The gate of second NMOS source transistor can be controlled in a number of ways, such as by a pulse, or a combination of pulse and mode entry and/or exit signals.
An embodiment of the invention describes a dynamic memory (DRAM) device, comprising: (a) a plurality of memory cells whose memory state is maintained in response to performing refresh operations; (b) a pair of bitlines coupled to the memory cells; (c) a bitline sense amplifier coupled to the bitlines for sensing the state of the memory cells; and (d) a plurality of source transistors coupled to the bitline sense amplifier and configured to increase the voltage potential of memory cell high data.
By way of example, the plurality of source transistors can comprise three source transistors. In one case the source transistors comprise a first PMOS source transistor, and a first and second NMOS source transistor. The source transistors are connected to a latch within the bitline sense amplifier. A first of the plurality of source transistors is used to speed up supply power by being connected to a power supply configured with a higher voltage potential than the supply voltage of a second source transistor and a third source transistor within the plurality of source transistors. In this case the second source transistor can be configured to deliver main power, and the third source transistor to deliver auxiliary power.
An embodiment describes a method of reducing current in a dynamic memory circuit, comprising: (a) coupling at least one source transistor to the sense amplifiers of the dynamic memory circuit for operation from virtual power supplies; (b) suspending read and/or write accesses to a memory block to enter active-standby mode in response to receiving an associated signal; and (c) changing the state of the source transistors while maintaining data in the memory cell to reduce operating current of the memory block.
In one implementation the source transistors comprise at least one power source transistor, at least one ground source transistor, or a combination of power and ground source transistors. The source transistors are controlled in response to device signals, such as receiving a pulse signal, or a reference voltage received through an error detector, or mode entry and/or exit signals, or a combination of pulse, reference voltage, or mode entry and/or exit signals. Changing the state of the source transistors lowers the voltage supplied to the bitline latch in active standby mode.
The source transistors can be configured in different ways. In one case the source transistor comprises at least one NMOS source transistor, or at least one PMOS source transistor, or a combination of NMOS and PMOS source transistors. For example, the source transistor can comprise at least one NMOS power source transistor configured with a gate potential that is lower when the dynamic memory circuit is in active standby mode than when the dynamic memory circuit is in normal operating mode. The source transistor can comprise at least a ground source transistor which supplies ground voltage to the bitline latch wherein the ground voltage has a higher potential in active standby mode than in normal operating mode in response to controlling the state of the ground source transistor. The ground source transistor can comprise NMOS source transistors, PMOS source transistors, or both NMOS and PMOS source transistors.
An embodiment of the present invention describes a method of reducing current in a dynamic memory circuit, comprising: (a) coupling at least one source transistor to the sense amplifier of the dynamic memory circuit to configure it for operation from a virtual power supply; and (b) changing the state of the at least one source transistor to reduce operating current of the memory block while maintaining data in the memory cell; (c) receiving an asynchronous signal (i.e., command signal) with positive setup time relative to a first clock, or a synchronous signal reference to a second clock with a positive setup time relative to the first clock, to change the state of the source transistor(s). In one case the second clock and the first clock operate at an identical frequency, while having a differing phase relationship. In another case the second clock and the first clock operate at different frequencies.
In one implementation of this method the source transistors comprise power source transistors, for example, as a combination of NMOS and/or PMOS source transistors. By way of example, two or more asynchronous signals can control the power source transistors, with the earlier asynchronous signal being applied to the gate of the PMOS source transistor. The asynchronous signal that enables the NMOS source transistor has a voltage potential that exceeds the power potential.
In one implementation of this method the source transistors comprise ground source transistors, for example a combination of NMOS and/or PMOS transistors. For example, the source transistors can comprise ground source transistors. Two or more asynchronous signals control the ground source transistors and the earlier asynchronous signal is applied to the gate of the NMOS source transistor and the later signal applied to the PMOS transistor. The asynchronous signal that enables the PMOS source transistor has a voltage potential below that of ground potential.
Other implementations are also described, such as the control of power source transistors and ground source transistors using synchronous signals, or a combination of asynchronous and synchronous signals.
An embodiment describes a method of reducing current in a dynamic memory circuit, comprising: (a) coupling at least one source transistor to the sense amplifier of the dynamic memory circuit to configure it for operation from a virtual power supply; and (b) changing the state of the at least one source transistor to reduce operating current of the memory block while maintaining data in the memory cell; (c) wherein the state of the source transistor is changed in response to receiving an asynchronous signal with positive setup time relative to a clock and a synchronous signal (i.e., command) referenced to the same clock.
In addition, the dynamic memory circuit can be logically or physically divided into sections in which source transistors of a first portion of these sections are controlled by an asynchronous signal and source transistors of a second portion of the sections are controlled by a synchronous signal. Different combinations are described of synchronous and asynchronous control as well as the transistor being used.
An embodiment describes a integrated circuit, comprising: (a) at least one block of memory cells containing a plurality of logic transistors; (b) at least one power path and at least one ground path bordering the block of memory cells; (c) a row decoder coupled to each block of memory cells within the at least one block of memory cells; (d) a column decoder coupled to each block of memory cells within the at least one block of memory cells; (e) at least a pair of bitlines coupled to each memory cell of the at least one block of memory cells; (f) a bit line sense amplifier coupled to the pair of bit lines and configured for sensing differential voltage of a memory cell within the memory cells and refreshing the high or low state of the memory cell; (g) at least one source transistor within the plurality of logic transistors of the memory block which is configured for generating at least one virtual voltage level; and (h) at least one virtual power path, virtual ground path, or combination of virtual power and ground paths coupled to the at least one virtual voltage level.
In the layout of this integrated circuit at least one source transistor can be placed closer to its respective power or ground line than the logic transistors. The source transistor can comprise a power source transistor, a ground source transistor, or a combination of power and ground source transistors. In one case the power source transistor includes an NMOS source transistor, or the ground source transistor includes a PMOS source transistor, or both power and ground source transistors can be included.
The source transistors can be positioned outside of the memory block, which is composed of logic transistors. An embodiment describes an integrated circuit in which the source transistor is positioned under the power line and does not cross the plurality of logic transistors of the block of memory cells. Implementations describe source transistor placement comprising a lumped placement of source transistors for the entire logic block, or a distributed placement where power and source transistors are adjacent to each layout block. The source transistors can comprise any combination of power source transistors and ground source transistors which drive the entire layout block. Alternatively, the block of memory cells can be segmented and power and/or ground source transistors placed per each segment.
The source transistors can generate a potential on a virtual power line, such as one that is positioned closer to the logic transistors of the memory cells than to one or more power lines of the integrated circuit. In one implementation the source transistors are positioned in the gap between a pair of column decoders at the intersection of a sub-wordline driver, or by strapping. In other implementations source transistors are positioned in the gap between row decoders, such as at the intersection with a bitline sense amplifier. The source transistor can be positioned in the gap between a first and second sub-wordline driver at the intersection with a bitline sense amplifier. Source transistors can comprise a PMOS source transistor placed in an NWELL of a cross-coupled pair of PMOS transistors within a latch of the bit line sense amplifier, or the source transistor can comprise an NMOS power source transistor placed in a PWELL, or on a portion of P-type substrate. The source transistors can be placed on each pair of bitlines or a group of bitline pairs.
An embodiment of the invention describes a method of determining proper source transistor connection within a memory or logic circuit, comprising: (a) executing a simulation routine for characterizing the memory or logic circuit; (b) assigning a known state, other than VDD or VSS, to the node where a source transistor connects to the logic transistor during the simulation, wherein the known state is output at the logic output for a predetermined input state.
An aspect of the invention is reducing leakage current in memory circuits, and in particular dynamic memory circuits subject to refresh.
Another aspect of the invention is the incorporation of various source transistor configurations for providing virtual source and virtual ground potentials to provide power for portions of the circuit in response to operating mode.
Another aspect of the invention is that of reducing standby currents, such as active power-down standby (ICC3P), by incorporating select source transistor configurations.
Another aspect of the invention is to reduce leakage that arises from duplicated circuits, such as row decoders, wordline drivers and so forth, wherein these circuits are deactivated after storing state information that is utilized to reload the circuits upon reactivation.
Another aspect of the invention is to provide different circuits for controlling source transistors to drive virtual power lines.
Another aspect of the invention provides layout methods for enhancing the use of power source transistors while minimizing the chip area used.
A still further aspect of the invention is a method of verifying source transistor use during integrated circuit design and layout.
Further aspects of the invention will be brought out in the following portions of the specification, wherein the detailed description is for the purpose of fully disclosing preferred embodiments of the invention without placing limitations thereon.
The invention will be more fully understood by reference to the following drawings which are for illustrative purposes only:
Referring more specifically to the drawings, for illustrative purposes the present invention is embodied in the apparatus generally shown in
1. Methods to Reduce Self-Refresh Current.
However, when memory cell C0 is accessed, a significant leakage current path for MNA1 is formed. After wordline WL0 is activated and charge between memory cell C0 and bitline BL_R is shared, the bitline sense amplifier pairs consisting of MPS1, MPS2, MNS1 and MNS2 detect and amplify the developed signal difference at bitline pair BL and BLB. As a consequence of the data stored at memory cell C0 being low, BL_R goes to low (VSS) and BLB_R goes to high (VDD). At this point, while VGD of MNA1 is still −VDD, VGS of MNA1 is zero instead of −½ *VDD as in the precharge state. Due to the absence of reverse bias condition for VGS of MNA1, the leakage current through MNA1 increases significantly and therefore, data retention time for stored high data at NS1 can be subject to drastic reduction. This leakage current represents a serious problem in DRAM operation modes, such as self-refresh mode, because the DRAM cell refresh period is determined purely based on how long the data can be stored at a memory cell and the longer the refresh period the smaller the refresh current. This self-refresh current therefore is an important parameter for low power devices such as mobile application devices.
Circuits and methods are described herein which suppress leakage current in memory cells that are not being accessed. It should be appreciated that the voltage levels described are provided by way of example for one particular embodiment, wherein one of ordinary skill in the art will appreciate that the circuits and methods can be implemented to support any desired voltage potential for the power line.
In a first method, the wordline level is maintained at a slightly lower voltage than zero. For example, in a precharge state, the wordline level is set to −0.3V instead of 0V. When a memory cell is accessed, even though the bitline voltage is developed to VSS, the VGS of memory access transistors which are not accessed is not 0V, but is −0.3V. One disadvantage of this method is the requirement of a negative voltage in self-refresh mode and the difficulty in achieving a lower voltage such as −0.6V to further suppress leakage current in self-refresh mode.
In a second method, a developed bitline level is boosted while maintaining the wordline voltage to be zero so that VGS of the memory access transistor is a negative value. One way to achieve this is to discharge the bitline to a voltage higher than 0V, instead of discharging to VSS. For example, when the memory array is accessed, the bitline BL_R is discharged to 0.3V instead of to VSS which is normally at 0V. Therefore, even though the wordline level of an un-accessed memory cell is zero, VGS of the corresponding memory access transistor is −0.3V.
Clamping of the bitline voltage can be achieved by any suitable means, one such mechanism is represented in
A disadvantage of boosting the developed bitline level is slower sensing speed of the sense amplifier. For example, assume that the bitline pairs are set to half VDD (1V) and node LAb is boosted by a certain voltage (0.3V) instead of its normal value of 0V. Without boosting, VGS of MNS1 can be ½*VDD (1V) when a sensing operation starts, but with boosting it can only be 0.7V. As such, the reduced current capability of the sensing transistor can degrade the sensing speed. To overcome this shortcoming, a novel power boosting scheme is disclosed herein. In normal operation, the DRAM core voltages are VDD and VSS. In self-refresh mode, the DRAM core voltages are VDDH and VSSH, where VDDH and VSSH are power and ground voltages boosted by a certain amount, respectively.
A necessary assumption here is that the DRAM core voltage VDD can be higher in self-refresh mode than in normal operating mode. For example, VDD is 2V in normal operating mode and 2.5V in self-refresh mode. If a PMOS transistor is used for the power source transistor, the period to enable the PMOS power source transistor can be longer to supply more current to the sense amplifier. Therefore, BLB_R goes to a higher voltage (VDDH) than normal operation. SAN goes to VSS instead of VBBZ and the level of BL_R is clamped at VTP (i.e., VSSH voltage level) of the PMOS source transistor MPSRC1 instead of VSS. Therefore, when WL0 is activated and the memory cell, C0, is read out. It should be noted that because BL_R is not VSS but is VSSH instead, then VGS of MNA1 is not zero, but is −VSSH and leakage current is suppressed significantly. When the sensing operation is finished and bitline pairs are equalized, the bitline precharge level is now not at ½ VDD but is at the higher voltage of ½ *VDDH. Consequently, as VGS of NMOS transistor MNS1 is not reduced the device is not subject to any sensing speed degradation.
There are a number of ways according to the present invention to control the voltage levels at nodes LA and LAb. The methods below are provided by way of example and not limitation.
Controlling Voltage Levels at Node LA.
When a PMOS transistor is used for the power source transistor, the period to turn on the PMOS transistor is preferably extended to supply a higher voltage to the sense amplifier by either controlling a pulse, in response to mode entry and/or exit signals, to enable the PMOS transistor or directly utilizing a mode entry and/or exit signal. By way of example and not limitation, two different source transistor types (pure PMOS and PMOS with a diode) can be utilized. In normal operation, the pure PMOS transistor and/or PMOS with a diode, can be turned on in normal operation while only the PMOS transistor with the diode can be turned on in self-refresh mode.
When an NMOS transistor is used for the power source transistor, the gate voltage can be controlled (e.g., a higher voltage than normal operation) to supply a higher voltage to the sense amplifier in the form of a pulse width or a mode entry and/or exit signal.
Controlling Voltage Levels at Ground Level.
When a PMOS transistor is used for the ground source transistor, the gate voltage can be applied so as not to overcome the PMOS threshold voltage drop, e.g., VSS instead of VBBZ. The gate can be controlled utilizing a form of pulse, or a mode entry and/or exit signal, or a combination of signals.
When an NMOS transistor is used for a ground source transistor, the period required to turn on the NMOS transistor can be controlled so as to be shorter, thereby preventing ground level discharging to VSS. This period can be controlled in the form of a pulse, or a mode entry and/or exit signal, or a signal combination. In a preferred embodiment, two different source transistor types (pure NMOS and NMOS with a diode) can be used. In normal operation, the pure NMOS transistor and/or NMOS transistor with a diode can be turned on in normal operation, while only the NMOS transistor with a diode can be turned on in self-refresh mode to clamp VSS at VDIODE.
A third method utilizes a combination of the two methods above, a negative wordline scheme and new bitline level control scheme. When this method is used, the circuit modifications to implement the method is not as complex or difficult as using only one of the two above mentioned methods. In this method, by not lowering a precharge wordline level as much as the first method, the design complexity can be reduced, and by not boosting the bitline level as much as the second method, the sensing speed is not significantly compromised and the power level does not need to be boosted as much. This lower level of voltage boosting is important, because as the operating voltage is reduced, there becomes no appreciable difference between the external voltage and the internal DRAM core operating voltage.
2. Methods to Reduce ICC3P Current.
One important parameter in DRAM operation is ICC3P mode, which is an operating mode referred to as “active power-down standby mode”. In the ICC3P mode a memory bank is activated and CKE (clock enable signal) is low (disabled) and CSB is high (disabled) but address and control inputs are switching, while the data bus inputs are stable. In response to this mode of operation the sense amplifier shown in
It should be appreciated that power and ground source transistors may be different from
By way of example, the combination of source transistors include: NMOS power source transistor and PMOS ground source transistor, NMOS power source transistor and NMOS ground source transistor, PMOS power source transistor and NMOS power source transistor, PMOS power source transistor and PMOS ground source transistor, NMOS and PMOS power/ground source transistors, NMOS and PMOS power source transistors and NMOS power source transistor, and so forth. According to this aspect of the invention, when the chip operates in ICC3P mode, source transistors connected to such repeated circuits as row decoders and wordline drivers are turned off to suppress leakage current.
According to one aspect of the invention, instead of maintaining the state of the wordlines, the wordline (state) information is stored in a circuit as the wordlines are turned off and retrieved as the wordlines are turned back on again. According to one implementation, the wordline information is stored at the output of pre-decoders in the pre-decoding signal latches as shown in
It should be appreciated that the voltage levels of the sensing nodes can be lowered through the use of any desired transistor types for each sensing node, for example: NMOS for power source and PMOS for ground source, PMOS for power source and NMOS for ground source, or NMOS for power source and NMOS for ground source, and so forth. It should be noted that in the example of
When the ICC3P mode starts, higher VT transistors in row decoders and wordline drivers are turned on while higher performance transistors (normal or low VT transistors) are turned off. The levels of sensing nodes (LA and LAb in
When the ICC3P mode is entered, the source transistors are connected to row decoders and the wordline drivers are turned off and the wordline information is stored at the output of row pre-decoders or row decoders. The power and ground source transistors of bitline sense amplifiers are turned off. When the ICC3P mode is finished, the wordline is reactivated and the power and ground source transistors of bitline sense amplifiers are turned on to restore the levels of sensing nodes to normal levels (VCORE and VSS, respectively) and the cell data is refreshed.
3. Methods for Early Wake-Up.
Source transistors are added to a circuit block implemented with low VT transistors to improve speed and reduce leakage current by shutting off source transistors. Some example combinations of power/ground source transistors according to the present invention can include NMOS/PMOS, NMOS/NMOS, PMOS/PMOS, PMOS/NMOS, NMOS & PMOS/PMOS & NMOS. The gate voltages of the source transistors can be varied from VPPZ to VBBZ according to the specific applications. Therefore, in source transistor circuit configurations according to the invention, the control of source transistors is critical wherein it is often appropriate to utilize different control methods depending on circuit application.
A first method of controlling the source transistors is to turn them on at the rising or falling clock edge of command information. For example, when the clock falling edge is used to accept a command, source transistors can be turned on after determining if the command is valid. However, in this case, since the virtual power and ground levels such as potentials at VDDZ and VSSZ in
Referring again to
At the rising edge of the clock, an internal clock and an internal synchronous signal N2 are generated. When the internal clock is generated, the state of the command is valid (low for this figure), and the control signal PES maintains the valid state. If a command is received by the chip, such as a precharge command, the internal asynchronous signal N1 is not generated (high in the second clock of this figure), because this command does not activate the chip. At the rising edge of the clock, the internal clock is generated, yet because the state of N1 is not valid, internal synchronous signal N2 is disabled (it goes to high). The control signal PES is also disabled (low for this figure) and source transistors are turned off. It should be appreciated that the described circuit provides a means to enable source transistors earlier than the arrival of the clock signal and to control them based on command state.
In some applications, the chip allows command switching but is in an idle or don't-care condition. In this case, even though there is no specific chip operation, the source transistors repeatedly turn on and off, wherein power is consumed unnecessarily due to repeated capacitive charging and discharging. To reduce power consumption due to unnecessary switching, an aspect of the invention teaches another method for controlling power source transistors.
There are a number of important aspects which have been discussed so far, the following provided by way of partial summary. Generating a wake-up signal to enable source transistors based on a signal received earlier than the clock signal. The state of the wake-up signal can be determined by a command at the clock edge. Different wake-up signals can be generated to control different circuit blocks depending on signal timing flow. An early wake-up signal can be generated to enable source transistors to activate the source transistors earlier than the clock using asynchronous information of command and synchronous commands referenced to the clock. A late wake-up signal can be generated with command and clock information to prevent unnecessary switching power consumption due to unnecessary turning on and off of source transistors. The early wake-up signal is applied to the circuits at early timing stages and the late wake-up signal is applied to the circuits at a late timing stage. Each control signal can have proper levels and polarities for different source transistor types
4. Methods to Control Source Transistors.
In the case shown, EVC is the external supply voltage and IVC is internally generated voltage. The control signal SAP2 turns on for a certain period to VPPZ2 level which is sufficiently high to turn on the NMOS transistor. This transistor helps to quickly charge the virtual power line because it is connected to EVC, meaning that a large amount of current can flow. The NMOS transistor controlled by signal SAP1 also charges the virtual power line at the same time and establishes the final voltage of the virtual power line due to the stable nature of IVC. An important function of the PMOS transistor, besides charging the virtual power line, is to make sure that the final virtual power line voltage is as intended in case VPPZ1 fails to reach a sufficiently high voltage due to circuit malfunction, environmental effects, process variation, and so forth. The PMOS transistor only requires a VSS voltage level to allow it to fully turn on so it will make sure that the virtual power line voltage is established at the proper level. This example shows control signals SAPB1, SAP1, and SAP2 turning on at the same time but they may turn on in any combination in other applications.
5. Layout Guidelines.
The following section describes unit layout, block layout and core layout according to an aspect of the present invention which is referred to as z-logic.
The layout method provides for placing at least one power/ground source transistor inside a layout block composed of logic transistors. For example, at least one power/ground source transistor is placed closer to power/ground line than the logic transistors. It should be appreciated that this may be implemented with: (1) the power source transistor including at least one NMOS transistor, (2) the ground source transistor including a PMOS transistor, (3) the power source transistor including at least one NMOS transistor and the ground source transistor including at least one PMOS transistor, (4) the power source transistor including NMOS and PMOS transistors, or (5) the ground source transistor including a PMOS transistor and an NMOS transistor.
The method also describes placing at least one power/ground source transistor outside the layout block composed of logic transistors. In one embodiment the source transistor is placed under the power lines that do not cross the layout block composed of logic transistors. The source transistors can be comprised as (1) through (5) listed above. In addition, the source transistors can be lumped for the entire logic block or any desired portion thereof. In one embodiment the source transistors can be placed in a distributed manner wherein the power and source transistors are located adjacent to each layout block. In one implementation a power source transistor and a ground source transistor drive the entire layout block. In one implementation the layout block is segmented and a power source transistor and a ground source transistor is placed per each segment.
Described according to an aspect of the invention is the placement of a virtual power line, which is a power line that connects source transistors to logic transistors, closer to the logic transistor than to the power line.
In one implementation source transistors are placed in the gap between column decoders created by sub-wordline drivers or strapping. Alternatively, the source transistors can be placed in the gap between row decoders created by the bitline sense amplifier. As another alternative, the source transistors that pertain to bitline sense amplifiers can be placed in the gap between sub-wordline drivers created by bitline sense amplifiers.
In one embodiment of bitline sense amplifier for a DRAM, a PMOS ground source transistor for an NMOS latch is placed in the NWELL of a PMOS latch. Similarly, an NMOS power source transistor for a PMOS latch can be placed in a PWELL, or P-type substrate, of an NMOS latch.
In one embodiment of DRAM, source transistors are placed on each bitline pair or group of bitline pairs.
6. Path Finder Source Transistor Checking.
A method is described for checking proper source transistor connection by assigning a known state other than VDD or VSS to the node where source transistor connects to the logic transistor and this known state is output at the logic output for a certain input state. By way of example the known state may be a Hi-z state, or a known state defined in standby mode. In one implementation the same type of source transistors are connected at every other logic gate.
According to one implementation the method includes pin property assignment, and port properties taken from the schematic itself, external text files or the port name.
In one implementation, a method is described to find a leakage path or circuit misconnection by comparing logic state on either side of the transmission gate.
A path finder method according to the present invention is described, which is referred to herein as z-technology. In using z-technology in a circuit whose standby status is already known by the designer, such as in DRAM circuits, the designer already knows the value of input/output ports and the value of internal nodes in blocks. In this case a zigzag style z-logic gate is utilized. By using zigzag style z-logic gates, all nodes must be set to their own standby value when the block is at standby mode. The leakage path occurrence condition can be found by running a simulator (i.e., Verilog simulation) with z-logic gates modeled as switch level.
Although the description above contains many details, these should not be construed as limiting the scope of the invention but as merely providing illustrations of some of the presently preferred embodiments of this invention. Therefore, it will be appreciated that the scope of the present invention fully encompasses other embodiments which may become obvious to those skilled in the art, and that the scope of the present invention is accordingly to be limited by nothing other than the appended claims, in which reference to an element in the singular is not intended to mean “one and only one” unless explicitly so stated, but rather “one or more.” All structural and functional equivalents to the elements of the above-described preferred embodiment that are known to those of ordinary skill in the art are expressly incorporated herein by reference and are intended to be encompassed by the present claims. Moreover, it is not necessary for a device or method to address each and every problem sought to be solved by the present invention, for it to be encompassed by the present claims. Furthermore, no element, component, or method step in the present disclosure is intended to be dedicated to the public regardless of whether the element, component, or method step is explicitly recited in the claims. No claim element herein is to be construed under the provisions of 35 U.S.C. 112, sixth paragraph, unless the element is expressly recited using the phrase “means for.”
This application claims priority from U.S. provisional application Ser. No. 60/720,185 filed on Sep. 23, 2005 incorporated by reference herein in its entirety.
| Number | Date | Country | |
|---|---|---|---|
| 60720185 | Sep 2005 | US |
