Nam Sung Kim

Person

Portland, OR, US

People

Patents Grantslast 30 patents

Information Patent Grant
Sequential circuit with error detection
- Patent number 10,024,916
- Issue date Jul 17, 2018
- Intel Corporation
- Keith A. Bowman
- G01 - MEASURING TESTING
Information Patent Grant
Sequential circuit with error detection
- Patent number 9,594,625
- Issue date Mar 14, 2017
- Intel Corporation
- Keith A. Bowman
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Sequential circuit with error detection
- Patent number 9,189,014
- Issue date Nov 17, 2015
- Intel Corporation
- Keith A. Bowman
- G01 - MEASURING TESTING
Information Patent Grant
Memory cell supply voltage control based on error detection
- Patent number 8,769,376
- Issue date Jul 1, 2014
- Intel Corporation
- Muhammad Khellah
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory cell supply voltage control based on error detection
- Patent number 8,667,367
- Issue date Mar 4, 2014
- Intel Corporation
- Muhammad Khellah
- G11 - INFORMATION STORAGE
Information Patent Grant
Sequential circuit with error detection
- Patent number 8,301,970
- Issue date Oct 30, 2012
- Intel Corporation
- Keith Bowman
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Memory cell supply voltage control based on error detection
- Patent number 8,006,164
- Issue date Aug 23, 2011
- Intel Corporation
- Khellah Muhammad
- G11 - INFORMATION STORAGE
Information Patent Grant
Sleep transistor array apparatus and method with leakage control ci...
- Patent number 7,812,631
- Issue date Oct 12, 2010
- Intel Corporation
- Nam Sung Kim
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Delay fault detection using latch with error sampling
- Patent number 7,653,850
- Issue date Jan 26, 2010
- Intel Corporation
- James W. Tschanz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory cell bit valve loss detection and restoration
- Patent number 7,653,846
- Issue date Jan 26, 2010
- Intel Corporation
- Nam Sung Kim
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory having bit line with resistor(s) between memory cells
- Patent number 7,558,097
- Issue date Jul 7, 2009
- Intel Corporation
- Muhammad M. Khellah
- G11 - INFORMATION STORAGE
Information Patent Grant
Sense amplifier method and arrangement
- Patent number 7,532,528
- Issue date May 12, 2009
- Intel Corporation
- Dinesh Somasekhar
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory with dynamically adjustable supply
- Patent number 7,403,426
- Issue date Jul 22, 2008
- Intel Corporation
- Fatih Hamzaoglu
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory cell having p-type pass device
- Patent number 7,230,842
- Issue date Jun 12, 2007
- Intel Corporation
- Muhammad M. Khellah
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
SEQUENTIAL CIRCUIT WITH ERROR DETECTION
- Publication number 20170139006
- Publication date May 18, 2017
- Intel Corporation
- Keith A. Bowman
- G01 - MEASURING TESTING
Information Patent Application
SEQUENTIAL CIRCUIT WITH ERROR DETECTION
- Publication number 20160034338
- Publication date Feb 4, 2016
- Intel Corporation
- Keith A. Bowman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Sequential Circuit with Error Detection
- Publication number 20140122947
- Publication date May 1, 2014
- Keith A. Bowman
- G01 - MEASURING TESTING
Information Patent Application
MEMORY CELL SUPPLY VOLTAGE CONTROL BASED ON ERROR DETECTION
- Publication number 20130024752
- Publication date Jan 24, 2013
- Muhammad Khellah
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY CELL SUPPLY VOLTAGE CONTROL BASED ON ERROR DETECTION
- Publication number 20110307761
- Publication date Dec 15, 2011
- Intel Corporation
- Khellah Muhammad
- G11 - INFORMATION STORAGE
Information Patent Application
Sequential circuit with error detection
- Publication number 20100079184
- Publication date Apr 1, 2010
- Keith Bowman
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
SENSE AMPLIFIER METHOD AND ARRANGEMENT
- Publication number 20090003108
- Publication date Jan 1, 2009
- Dinesh Somasekhar
- G11 - INFORMATION STORAGE
Information Patent Application
Method and apparatus improving performance of a digital memory arra...
- Publication number 20090006742
- Publication date Jan 1, 2009
- Min Huang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DELAY FAULT DETECTION USING LATCH WITH ERROR SAMPLING
- Publication number 20080307277
- Publication date Dec 11, 2008
- James W. Tschanz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Memory cell bit valve loss detection and restoration
- Publication number 20080162986
- Publication date Jul 3, 2008
- Intel Corporation
- Nam Sung Kim
- G11 - INFORMATION STORAGE
Information Patent Application
Memory having bit line with resistor(s) between memory cells
- Publication number 20080158932
- Publication date Jul 3, 2008
- Intel Corporation
- Muhammad M. Khellah
- G11 - INFORMATION STORAGE
Information Patent Application
Address hashing to help distribute accesses across portions of dest...
- Publication number 20080162869
- Publication date Jul 3, 2008
- Intel Corporation
- Nam Sung Kim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ANALOG PHASE CONTROL CIRCUIT AND METHOD
- Publication number 20080136507
- Publication date Jun 12, 2008
- Nam Sung Kim
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Memory cell supply voltage control based on error detection
- Publication number 20080082899
- Publication date Apr 3, 2008
- Intel Corporation
- Khellah Muhammad
- G11 - INFORMATION STORAGE
Information Patent Application
Memory driver circuits with embedded level shifters
- Publication number 20080080266
- Publication date Apr 3, 2008
- Muhammad M. Khellah
- G11 - INFORMATION STORAGE
Information Patent Application
Reducing aging effect on memory
- Publication number 20070271421
- Publication date Nov 22, 2007
- Nam Sung Kim
- G11 - INFORMATION STORAGE
Information Patent Application
Memory cell having p-type pass device
- Publication number 20070058419
- Publication date Mar 15, 2007
- Intel Corporation
- Muhammad M. Khellah
- G11 - INFORMATION STORAGE
Information Patent Application
Memory with dynamically adjustable supply
- Publication number 20060268626
- Publication date Nov 30, 2006
- Fatih Hamzaoglu
- G11 - INFORMATION STORAGE

Nam Sung Kim

Person

Patents Grantslast 30 patents

Sequential circuit with error detection

Sequential circuit with error detection

Sequential circuit with error detection

Memory cell supply voltage control based on error detection

Memory cell supply voltage control based on error detection

Sequential circuit with error detection

Memory cell supply voltage control based on error detection

Sleep transistor array apparatus and method with leakage control ci...

Delay fault detection using latch with error sampling

Memory cell bit valve loss detection and restoration

Memory having bit line with resistor(s) between memory cells

Sense amplifier method and arrangement

Memory with dynamically adjustable supply

Memory cell having p-type pass device

Patents Applicationslast 30 patents

SEQUENTIAL CIRCUIT WITH ERROR DETECTION

SEQUENTIAL CIRCUIT WITH ERROR DETECTION

Sequential Circuit with Error Detection

MEMORY CELL SUPPLY VOLTAGE CONTROL BASED ON ERROR DETECTION

MEMORY CELL SUPPLY VOLTAGE CONTROL BASED ON ERROR DETECTION

Sequential circuit with error detection

SENSE AMPLIFIER METHOD AND ARRANGEMENT

Method and apparatus improving performance of a digital memory arra...

DELAY FAULT DETECTION USING LATCH WITH ERROR SAMPLING

Memory cell bit valve loss detection and restoration

Memory having bit line with resistor(s) between memory cells

Address hashing to help distribute accesses across portions of dest...

ANALOG PHASE CONTROL CIRCUIT AND METHOD

Memory cell supply voltage control based on error detection

Memory driver circuits with embedded level shifters

Reducing aging effect on memory

Memory cell having p-type pass device

Memory with dynamically adjustable supply