Namerita Khanna

Person

New Delhi, IN

People

Patents Grantslast 30 patents

Information Patent Grant
Processing configuration data frames
- Patent number 7,774,682
- Issue date Aug 10, 2010
- Ashish Kumar Goel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Programmable logic devices
- Patent number 7,606,969
- Issue date Oct 20, 2009
- Davinder Aggarwal
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method and apparatus of reloading erroneous configuration data fram...
- Patent number 7,350,134
- Issue date Mar 25, 2008
- Sicronic Remote KG, LLC
- Ashish Kumar Goel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Architecture for programmable logic device
- Patent number 7,154,299
- Issue date Dec 26, 2006
- STMicroelectronics Pvt. Ltd.
- Parvesh Swami
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Programmable logic devices providing reduced power consumption
- Patent number 7,109,749
- Issue date Sep 19, 2006
- STMicroelectronics, Pvt. Ltd.
- Namerita Khanna
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
High performance interconnect architecture for field programmable g...
- Patent number 7,030,648
- Issue date Apr 18, 2006
- STMicroelectronics PVT, Ltd.
- Ankur Bal
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Low power clock distribution scheme
- Patent number 6,879,185
- Issue date Apr 12, 2005
- STMicroelectronics Pvt. Ltd.
- Parvesh Swami
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
DEVICE WITH LOW-POWER SYNCHRONIZING CIRCUITRY AND RELATED METHOD
- Publication number 20230062144
- Publication date Mar 2, 2023
- STMicroelectronics International N.V.
- Ankur BAL
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Programmable logic devices
- Publication number 20050172070
- Publication date Aug 4, 2005
- STMicroelectronics Pvt. Ltd.
- Davinder Aggarwal
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
High performance interconnect architecture for field programmable g...
- Publication number 20040178821
- Publication date Sep 16, 2004
- STMicroelectronics Pvt. Ltd.
- Ankur Bal
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Method and apparatus of reloading erroneous configuration data fram...
- Publication number 20040153923
- Publication date Aug 5, 2004
- STMicroelectronics Pvt, Ltd.
- Ashish Kumar Goel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Programmable logic devices providing reduced power consumption
- Publication number 20040008055
- Publication date Jan 15, 2004
- STMicroelectronics Pvt. Ltd.
- Namerita Khanna
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Low power clock distribution scheme
- Publication number 20030218480
- Publication date Nov 27, 2003
- Indian ST (STMicroelectronics Pvt. Ltd.)
- Parvesh Swami
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Architecture for programmable logic device
- Publication number 20030214321
- Publication date Nov 20, 2003
- STMicroelectronics Pvt. Ltd.
- Parvesh Swami
- H03 - BASIC ELECTRONIC CIRCUITRY

Namerita Khanna

Person

Patents Grantslast 30 patents

Processing configuration data frames

Programmable logic devices

Method and apparatus of reloading erroneous configuration data fram...

Architecture for programmable logic device

Programmable logic devices providing reduced power consumption

High performance interconnect architecture for field programmable g...

Low power clock distribution scheme

Patents Applicationslast 30 patents

DEVICE WITH LOW-POWER SYNCHRONIZING CIRCUITRY AND RELATED METHOD

Programmable logic devices

High performance interconnect architecture for field programmable g...

Method and apparatus of reloading erroneous configuration data fram...

Programmable logic devices providing reduced power consumption

Low power clock distribution scheme

Architecture for programmable logic device