Ned D. Garinger

Person

Chandler, AZ, US

People

Patents Grantslast 30 patents

Information Patent Grant
On chip network
- Patent number 7,277,449
- Issue date Oct 2, 2007
- FREESCALE SEMICONDUCTOR, INC.
- Ned D. Garinger
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
On chip network that maximizes interconnect utilization between pro...
- Patent number 7,200,137
- Issue date Apr 3, 2007
- FREESCALE SEMICONDUCTOR, INC.
- Martin L. Dorr
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
On chip network with independent logical and physical layers
- Patent number 7,139,860
- Issue date Nov 21, 2006
- Freescale Semiconductor Inc.
- Gary A. Walker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Scalable on chip network
- Patent number 7,051,150
- Issue date May 23, 2006
- FREESCALE SEMICONDUCTOR, INC.
- Mark W. Naumann
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
On chip network with memory device address decoding
- Patent number 6,996,651
- Issue date Feb 7, 2006
- FREESCALE SEMICONDUCTOR, INC.
- Ned D. Garinger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Circuit and method for converting interrupt signals from level trig...
- Patent number 6,145,047
- Issue date Nov 7, 2000
- VLSI Technology Inc.
- Ned D. Garinger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Combined consective byte update buffer
- Patent number 5,892,978
- Issue date Apr 6, 1999
- VLSI Technology, Inc.
- Gabriel R. Munguia
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Decoupled refresh on local and system busses in a PC/at or similar...
- Patent number 5,465,339
- Issue date Nov 7, 1995
- VLSI Technology, Inc.
- Ned Garinger
- G11 - INFORMATION STORAGE
Information Patent Grant
Self-compensating output pad for an integrated circuit and method t...
- Patent number 5,365,130
- Issue date Nov 15, 1994
- VLSI Technology, Inc.
- Joseph Murray
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Delay-compensated output pad for an integrated circuit and method t...
- Patent number 5,336,940
- Issue date Aug 9, 1994
- VLSI Technology, Inc.
- Peter H. Sorrells
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Compensated digital delay semiconductor device with selectable outp...
- Patent number 5,281,874
- Issue date Jan 25, 1994
- VLSI Technology, Inc.
- Peter H. Sorrells
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Self-compensating digital delay semiconductor device with selectabl...
- Patent number 5,252,867
- Issue date Oct 12, 1993
- VLSI Technology, Inc.
- Peter H. Sorrells
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Variable frequency clock for a computer system
- Patent number 5,136,180
- Issue date Aug 4, 1992
- VLSI Technology, Inc.
- Kenneth P. Caviasca
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
Scalable on chip network
- Publication number 20040024946
- Publication date Feb 5, 2004
- Mark W. Naumann
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
On chip network with independent logical and physical layers
- Publication number 20040019730
- Publication date Jan 29, 2004
- Gary A. Walker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
On chip network with memory device address decoding
- Publication number 20040019733
- Publication date Jan 29, 2004
- Ned D. Garinger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
On chip network that maximizes interconnect utilization between pro...
- Publication number 20040017807
- Publication date Jan 29, 2004
- Martin L. Dorr
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
On chip network
- Publication number 20040017820
- Publication date Jan 29, 2004
- Ned D. Garinger
- H04 - ELECTRIC COMMUNICATION TECHNIQUE

Ned D. Garinger

Person

Patents Grantslast 30 patents

On chip network

On chip network that maximizes interconnect utilization between pro...

On chip network with independent logical and physical layers

Scalable on chip network

On chip network with memory device address decoding

Circuit and method for converting interrupt signals from level trig...

Combined consective byte update buffer

Decoupled refresh on local and system busses in a PC/at or similar...

Self-compensating output pad for an integrated circuit and method t...

Delay-compensated output pad for an integrated circuit and method t...

Compensated digital delay semiconductor device with selectable outp...

Self-compensating digital delay semiconductor device with selectabl...

Variable frequency clock for a computer system

Patents Applicationslast 30 patents

Scalable on chip network

On chip network with independent logical and physical layers

On chip network with memory device address decoding

On chip network that maximizes interconnect utilization between pro...

On chip network