Neng-Tai Shih

Person

Taipei, TW

People

Patents Grantslast 30 patents

Information Patent Grant
Method of forming RRAM structure
- Patent number 8,999,733
- Issue date Apr 7, 2015
- Nanya Technology Corp.
- Chun-I Hsieh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Resistive random access memory structure with tri-layer resistive s...
- Patent number 8,901,527
- Issue date Dec 2, 2014
- Nanya Technology Corp.
- Chun-I Hsieh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
RRAM with improved resistance transformation characteristic and met...
- Patent number 8,487,290
- Issue date Jul 16, 2013
- Nanya Technology Corp.
- Chun-I Hsieh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit structure and method of forming the same
- Patent number 8,455,984
- Issue date Jun 4, 2013
- Nanya Technology Corp.
- Kee Wei Chung
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Single-sided access device and fabrication method thereof
- Patent number 8,395,209
- Issue date Mar 12, 2013
- Nanya Technology Corp.
- Hsin-Jung Ho
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for forming a semiconductor device with a single-sided burie...
- Patent number 7,993,985
- Issue date Aug 9, 2011
- Nanya Technology Corp.
- Neng-Tai Shih
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Trench-type semiconductor device structure
- Patent number 7,985,998
- Issue date Jul 26, 2011
- Nanya Technology Corp.
- Shian-Jyh Lin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Memory device and fabrication method thereof
- Patent number 7,759,190
- Issue date Jul 20, 2010
- Nanya Technology Corporation
- Neng-Tai Shih
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Memory device and fabrication method thereof
- Patent number 7,449,382
- Issue date Nov 11, 2008
- Nanya Technology Corporation
- Meng-Hung Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Dynamic random access memory
- Patent number 7,408,215
- Issue date Aug 5, 2008
- Nanya Technology Corp.
- Ming-Cheng Chang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of fabricating MOS transistor by millisecond anneal
- Patent number 7,160,804
- Issue date Jan 9, 2007
- Nanya Technology Corporation
- Shian-Jyh Lin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for forming a self-aligned buried strap in a vertical memory...
- Patent number 6,962,847
- Issue date Nov 8, 2005
- Nanya Technology Corporation
- Cheng-Chih Huang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for fabricating trench isolations with high aspect ratio
- Patent number 6,946,359
- Issue date Sep 20, 2005
- Nanya Technology Corporation
- Sheng-Wei Yang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for forming a self-aligned buried strap in a vertical memory...
- Patent number 6,927,123
- Issue date Aug 9, 2005
- Nanya Technology Corporation
- Cheng-Chih Huang
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
METHOD OF FORMING RRAM STRUCTURE
- Publication number 20150044852
- Publication date Feb 12, 2015
- NANYA TECHNOLOGY CORP.
- Chun-I Hsieh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SINGLE-SIDED ACCESS DEVICE AND FABRICATION METHOD THEREOF
- Publication number 20130075812
- Publication date Mar 28, 2013
- Hsin-Jung Ho
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT STRUCTURE AND METHOD OF FORMING THE SAME
- Publication number 20120119355
- Publication date May 17, 2012
- NANYA TECHNOLOGY CORP
- KEE WEI CHUNG
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
RRAM structure and method of making the same
- Publication number 20120001141
- Publication date Jan 5, 2012
- Chun-I Hsieh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
RRAM WITH IMPROVED RESISTANCE TRANSFORMATION CHARACTERISTIC AND MET...
- Publication number 20100072449
- Publication date Mar 25, 2010
- Chun-I Hsieh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TRENCH-TYPE SEMICONDUCTOR DEVICE STRUCTURE
- Publication number 20090166702
- Publication date Jul 2, 2009
- NANYA Technology Corp.
- Shian-Jyh LIN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR FORMING A SEMICONDUCTOR DEVICE WITH A SINGLE-SIDED BURIE...
- Publication number 20080268590
- Publication date Oct 30, 2008
- NANYA Technology Corp.
- Neng-Tai SHIH
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MEMORY DEVICE AND FABRICATION METHOD THEREOF
- Publication number 20080251829
- Publication date Oct 16, 2008
- NANYA TECHNOLOGY CORPORATION
- Neng-Tai Shih
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DYNAMIC RANDOM ACCESS MEMORY
- Publication number 20080029800
- Publication date Feb 7, 2008
- Ming-Cheng Chang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Memory device and fabrication method thereof
- Publication number 20070166914
- Publication date Jul 19, 2007
- NANYA TECHNOLOGY CORPORATION
- Meng-Hung Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
VERTICAL TRANSISTOR DEVICE AND FABRICATION METHOD THEREOF
- Publication number 20070131998
- Publication date Jun 14, 2007
- NANYA TECHNOLOGY CORPORATION
- Shian-Jyh Lin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Vertical transistor device and fabrication method thereof
- Publication number 20070096186
- Publication date May 3, 2007
- NANYA TECHNOLOGY CORPORATION
- Shian-Jyh Lin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method of fabricating MOS transistor by millisecond anneal
- Publication number 20060094178
- Publication date May 4, 2006
- NANYA TECHNOLOGY CORPORATION
- Shian-Jyh Lin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for forming a self-aligned buried strap in a vertical memory...
- Publication number 20050124111
- Publication date Jun 9, 2005
- NANYA TECHNOLOGY CORPORATION
- Cheng-Chih Huang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR FORMING A SELF-ALIGNED BURIED STRAP IN A VERTICAL MEMORY...
- Publication number 20050124110
- Publication date Jun 9, 2005
- NANYA TECHNOLOGY CORPORATION
- Cheng-Chih Huang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for fabricating trench isolations with high aspect ratio
- Publication number 20050016948
- Publication date Jan 27, 2005
- NANYA TECHNOLOGY CORPORATION
- Sheng-Wei Yang
- H01 - BASIC ELECTRIC ELEMENTS

Neng-Tai Shih

Person

Patents Grantslast 30 patents

Method of forming RRAM structure

Resistive random access memory structure with tri-layer resistive s...

RRAM with improved resistance transformation characteristic and met...

Integrated circuit structure and method of forming the same

Single-sided access device and fabrication method thereof

Method for forming a semiconductor device with a single-sided burie...

Trench-type semiconductor device structure

Memory device and fabrication method thereof

Memory device and fabrication method thereof

Dynamic random access memory

Method of fabricating MOS transistor by millisecond anneal

Method for forming a self-aligned buried strap in a vertical memory...

Method for fabricating trench isolations with high aspect ratio

Method for forming a self-aligned buried strap in a vertical memory...

Patents Applicationslast 30 patents

METHOD OF FORMING RRAM STRUCTURE

SINGLE-SIDED ACCESS DEVICE AND FABRICATION METHOD THEREOF

INTEGRATED CIRCUIT STRUCTURE AND METHOD OF FORMING THE SAME

RRAM structure and method of making the same

RRAM WITH IMPROVED RESISTANCE TRANSFORMATION CHARACTERISTIC AND MET...

TRENCH-TYPE SEMICONDUCTOR DEVICE STRUCTURE

METHOD FOR FORMING A SEMICONDUCTOR DEVICE WITH A SINGLE-SIDED BURIE...

MEMORY DEVICE AND FABRICATION METHOD THEREOF

DYNAMIC RANDOM ACCESS MEMORY

Memory device and fabrication method thereof

VERTICAL TRANSISTOR DEVICE AND FABRICATION METHOD THEREOF

Vertical transistor device and fabrication method thereof

Method of fabricating MOS transistor by millisecond anneal

Method for forming a self-aligned buried strap in a vertical memory...

METHOD FOR FORMING A SELF-ALIGNED BURIED STRAP IN A VERTICAL MEMORY...

Method for fabricating trench isolations with high aspect ratio