Ni Chung Cheng

Person

Hsin-chu, TW

People

Patents Grantslast 30 patents

Information Patent Grant
ZIF connectors and semiconductor testing device and system using th...
- Patent number 8,248,090
- Issue date Aug 21, 2012
- King Yuan Electronics Co., Ltd.
- Cheng-Chin Ni
- G01 - MEASURING TESTING
Information Patent Grant
Method for continuity test of integrated circuit
- Patent number 8,030,944
- Issue date Oct 4, 2011
- King Yuan Electronics Co., Ltd.
- Cheng-Chin Ni
- G01 - MEASURING TESTING
Information Patent Grant
Testing system module
- Patent number 8,008,938
- Issue date Aug 30, 2011
- King Yuan Electronics Co., Ltd.
- Cheng-Chin Ni
- G01 - MEASURING TESTING
Information Patent Grant
Parallel test fixture for mixed signal integrated circuits
- Patent number 7,821,277
- Issue date Oct 26, 2010
- King Yuan Electronics Co., Ltd.
- Cheng-Chin Ni
- G01 - MEASURING TESTING
Information Patent Grant
Probe card
- Patent number 7,804,315
- Issue date Sep 28, 2010
- King Yuan Electronics Co., Ltd.
- Cheng-Chin Ni
- G01 - MEASURING TESTING
Information Patent Grant
Probe card assembly and test probes therein
- Patent number 7,786,744
- Issue date Aug 31, 2010
- King Yuan Electronics Co., Ltd.
- Cheng-Chin Ni
- G01 - MEASURING TESTING
Information Patent Grant
Probe card
- Patent number 7,772,861
- Issue date Aug 10, 2010
- King Yuan Electronics Co., Ltd.
- Cheng-Chin Ni
- G01 - MEASURING TESTING
Information Patent Grant
Probe card assembly
- Patent number 7,710,134
- Issue date May 4, 2010
- King Yuan Electronics Co., Ltd.
- Cheng-Chin Ni
- G01 - MEASURING TESTING
Information Patent Grant
Probe card assembly and test probes therein
- Patent number 7,629,803
- Issue date Dec 8, 2009
- King Yuan Electronics Co., Ltd.
- Cheng-Chin Ni
- G01 - MEASURING TESTING
Information Patent Grant
Power metal oxide semiconductor field effect transistor layout
- Patent number 6,888,197
- Issue date May 3, 2005
- Mosel Vitelic, Inc.
- Cheng-Tsung Ni
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for forming dual oxide layers at bottom of trench
- Patent number 6,821,913
- Issue date Nov 23, 2004
- Mosel Vitelic, Inc.
- Chiao-Shun Chuang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of simultaneously implementing differential gate oxide thick...
- Patent number 6,784,115
- Issue date Aug 31, 2004
- Mosel Vitelic, Inc.
- Cheng-Tsung Ni
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Dynamic adjustment and auto generation of water per hour (WPH) in c...
- Patent number 6,662,066
- Issue date Dec 9, 2003
- Taiwan Semiconductor Manufacturing Company
- Lin Chien Yu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Fabricating a DMOS transistor
- Patent number 6,660,592
- Issue date Dec 9, 2003
- Mosel Vitelic, Inc.
- Chiao-Shun Chuang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
MOS transistors having dual gates and self-aligned interconnect con...
- Patent number 6,657,263
- Issue date Dec 2, 2003
- Mosel Vitelic, Inc.
- Cheng-Tsung Ni
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Flash cell device
- Patent number 6,563,166
- Issue date May 13, 2003
- Mosel Vitelic, Inc.
- Cheng-Tsung Ni
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
MOS transistors having dual gates and self-aligned interconnect con...
- Patent number 6,284,578
- Issue date Sep 4, 2001
- Mosel Vitelic, Inc.
- Cheng-Tsung Ni
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
MOS transistors having raised source and drain and interconnects
- Patent number 6,228,729
- Issue date May 8, 2001
- Mosel Vitelic, Inc.
- Cheng-Tsung Ni
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for fabricating MOS transistor having raised source and drain
- Patent number 6,150,244
- Issue date Nov 21, 2000
- Mosel Vitelic Inc.
- Cheng-Tsung Ni
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for fabricating MOSFET having increased effective gate length
- Patent number 6,127,699
- Issue date Oct 3, 2000
- Mosel Vitelic, Inc.
- Cheng-Tsung Ni
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Micro-trench oxidation by using rough oxide mask for field isolation
- Patent number 6,008,106
- Issue date Dec 28, 1999
- Mosel Vitelic Inc.
- Tuby Tu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for fabricating MOSFET having increased effective gate length
- Patent number 5,972,754
- Issue date Oct 26, 1999
- Mosel Vitelic, Inc.
- Cheng-Tsung Ni
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for preventing substrate damage during semiconductor fabrica...
- Patent number 5,804,493
- Issue date Sep 8, 1998
- Mosel Vitelic, Inc.
- Minn-Horng Juang
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
Probe Card
- Publication number 20100182028
- Publication date Jul 22, 2010
- King Yuan Electronics Co., Ltd.
- Cheng-Chin Ni
- G01 - MEASURING TESTING
Information Patent Application
ZIF CONNECTORS AND SEMICONDUCTOR TESTING DEVICE AND SYSTEM USING T...
- Publication number 20100164524
- Publication date Jul 1, 2010
- Cheng-Chin NI
- G01 - MEASURING TESTING
Information Patent Application
PROBE CARD ASSEMBLY AND TEST PROBES THEREIN
- Publication number 20100109689
- Publication date May 6, 2010
- Cheng-Chin Ni
- G01 - MEASURING TESTING
Information Patent Application
Probe Card
- Publication number 20100052710
- Publication date Mar 4, 2010
- Cheng-Chin Ni
- G01 - MEASURING TESTING
Information Patent Application
PROBE CARD ASSEMBLY
- Publication number 20090315577
- Publication date Dec 24, 2009
- Cheng-Chin NI
- G01 - MEASURING TESTING
Information Patent Application
PROBE CARD ASSEMBLY AND TEST PROBES THEREIN
- Publication number 20090315576
- Publication date Dec 24, 2009
- Cheng-Chin NI
- G01 - MEASURING TESTING
Information Patent Application
Parallel Test Fixture for Mixed Signal Integrated Circuits
- Publication number 20090260863
- Publication date Oct 22, 2009
- Cheng-Chin Ni
- G01 - MEASURING TESTING
Information Patent Application
METHOD FOR CONTINUITY TEST OF INTEGRATED CIRCUIT
- Publication number 20090251165
- Publication date Oct 8, 2009
- Cheng-Chin Ni
- G01 - MEASURING TESTING
Information Patent Application
TESTING SYSTEM MODULE
- Publication number 20090243643
- Publication date Oct 1, 2009
- Cheng-Chin Ni
- G01 - MEASURING TESTING
Information Patent Application
Testing system module
- Publication number 20090108862
- Publication date Apr 30, 2009
- Cheng-Chin Ni
- G01 - MEASURING TESTING
Information Patent Application
Method for accurate measuring stray capacitance of automatic test e...
- Publication number 20090093987
- Publication date Apr 9, 2009
- Cheng-Chin Ni
- G01 - MEASURING TESTING
Information Patent Application
Power metal oxide semiconductor field effect transistor layout
- Publication number 20040113205
- Publication date Jun 17, 2004
- MOSEL VITELIC, INC.
- Cheng-Tsung Ni
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Fabricating a DMOS transistor
- Publication number 20030096485
- Publication date May 22, 2003
- MOSEL VITELIC, INC.
- Chiao-Shun Chuang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for forming dual oxide layers at bottom of trench
- Publication number 20030068901
- Publication date Apr 10, 2003
- MOSEL VITELIC, INC.
- Chiao-Shun Chuang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MOS transistors having dual gates and self-aligned interconnect con...
- Publication number 20010049165
- Publication date Dec 6, 2001
- Mosel Vitelic, Inc.
- Cheng-Tsung Ni
- H01 - BASIC ELECTRIC ELEMENTS

Ni Chung Cheng

Person

Patents Grantslast 30 patents

ZIF connectors and semiconductor testing device and system using th...

Method for continuity test of integrated circuit

Testing system module

Parallel test fixture for mixed signal integrated circuits

Probe card

Probe card assembly and test probes therein

Probe card

Probe card assembly

Probe card assembly and test probes therein

Power metal oxide semiconductor field effect transistor layout

Method for forming dual oxide layers at bottom of trench

Method of simultaneously implementing differential gate oxide thick...

Dynamic adjustment and auto generation of water per hour (WPH) in c...

Fabricating a DMOS transistor

MOS transistors having dual gates and self-aligned interconnect con...

Flash cell device

MOS transistors having dual gates and self-aligned interconnect con...

MOS transistors having raised source and drain and interconnects

Method for fabricating MOS transistor having raised source and drain

Method for fabricating MOSFET having increased effective gate length

Micro-trench oxidation by using rough oxide mask for field isolation

Method for fabricating MOSFET having increased effective gate length

Method for preventing substrate damage during semiconductor fabrica...

Patents Applicationslast 30 patents

Probe Card

ZIF CONNECTORS AND SEMICONDUCTOR TESTING DEVICE AND SYSTEM USING T...

PROBE CARD ASSEMBLY AND TEST PROBES THEREIN

Probe Card

PROBE CARD ASSEMBLY

PROBE CARD ASSEMBLY AND TEST PROBES THEREIN

Parallel Test Fixture for Mixed Signal Integrated Circuits

METHOD FOR CONTINUITY TEST OF INTEGRATED CIRCUIT

TESTING SYSTEM MODULE

Testing system module

Method for accurate measuring stray capacitance of automatic test e...

Power metal oxide semiconductor field effect transistor layout

Fabricating a DMOS transistor

Method for forming dual oxide layers at bottom of trench

MOS transistors having dual gates and self-aligned interconnect con...