Nicholas R. Watts

Person

Phoenix, AZ, US

People

Patents Grantslast 30 patents

Information Patent Grant
Offset interposers for large-bottom packages and large-die package-...
- Patent number 12,107,082
- Issue date Oct 1, 2024
- Intel Corporation
- Russell K. Mortensen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Offset interposers for large-bottom packages and large-die package-...
- Patent number 11,978,730
- Issue date May 7, 2024
- Intel Corporation
- Russell K. Mortensen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Offset interposers for large-bottom packages and large-die package-...
- Patent number 11,798,932
- Issue date Oct 24, 2023
- Intel Corporation
- Russell K. Mortensen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Offset interposers for large-bottom packages and large-die package-...
- Patent number 10,607,976
- Issue date Mar 31, 2020
- Intel Corporation
- Russell K. Mortensen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Offset interposers for large-bottom packages and large-die package-...
- Patent number 10,446,530
- Issue date Oct 15, 2019
- Intel Corporation
- Russell K. Mortensen
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Passive within via
- Patent number 9,960,079
- Issue date May 1, 2018
- Intel Corporation
- Todd B. Myers
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor package with embedded die and its methods of fabrication
- Patent number 9,780,054
- Issue date Oct 3, 2017
- Intel Corporation
- John S. Guzek
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Pin grid interposer
- Patent number 9,607,937
- Issue date Mar 28, 2017
- Intel Corporation
- Nicholas R. Watts
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor package with embedded die and its methods of fabrication
- Patent number 8,901,724
- Issue date Dec 2, 2014
- Intel Corporation
- John Stephen Guzek
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Method of stiffening coreless package substrate
- Patent number 8,860,205
- Issue date Oct 14, 2014
- Intel Corporation
- Sriram Muthukumar
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Semiconductor device with package to package connection
- Patent number 7,952,182
- Issue date May 31, 2011
- Intel Corporation
- Nicholas Randolph Watts
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of embedding passive component within via
- Patent number 7,952,202
- Issue date May 31, 2011
- Intel Corporation
- Todd B Myers
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Method of stiffening coreless package substrate
- Patent number 7,851,269
- Issue date Dec 14, 2010
- Intel Corporation
- Sriram Muthukumar
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Via including multiple electrical paths
- Patent number 7,737,025
- Issue date Jun 15, 2010
- Intel Corporation
- Todd B Myers
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Method of embedding passive component within via
- Patent number 7,275,316
- Issue date Oct 2, 2007
- Intel Corporation
- Todd B Myers
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Via including multiple electrical paths
- Patent number 7,183,653
- Issue date Feb 27, 2007
- Intel Corporation
- Todd B Myers
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Multilayer capacitor, wiring board, decoupling circuit, and high fr...
- Patent number 6,606,237
- Issue date Aug 12, 2003
- Murata Manufacturing Co., Ltd.
- Yasuyuki Naito
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Electronic circuit housing with trench vias and method of fabricati...
- Patent number 6,556,453
- Issue date Apr 29, 2003
- Intel Corporation
- David G. Figueroa
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR

Patents Applicationslast 30 patents

Information Patent Application
OFFSET INTERPOSERS FOR LARGE-BOTTOM PACKAGES AND LARGE-DIE PACKAGE-...
- Publication number 20240222350
- Publication date Jul 4, 2024
- Intel Corporation
- Russell K. MORTENSEN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
OFFSET INTERPOSERS FOR LARGE-BOTTOM PACKAGES AND LARGE-DIE PACKAGE-...
- Publication number 20240006401
- Publication date Jan 4, 2024
- Intel Corporation
- Russell K. MORTENSEN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
OFFSET INTERPOSERS FOR LARGE-BOTTOM PACKAGES AND LARGE-DIE PACKAGE-...
- Publication number 20220344318
- Publication date Oct 27, 2022
- Intel Corporation
- Russell K. MORTENSEN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
OFFSET INTERPOSERS FOR LARGE-BOTTOM PACKAGES AND LARGE-DIE PACKAGE-...
- Publication number 20220157799
- Publication date May 19, 2022
- Intel Corporation
- Russell K. MORTENSEN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
OFFSET INTERPOSERS FOR LARGE-BOTTOM PACKAGES AND LARGE-DIE PACKAGE-...
- Publication number 20200251462
- Publication date Aug 6, 2020
- Intel Corporation
- Russell Mortensen
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
OFFSET INTERPOSERS FOR LARGE-BOTTOM PACKAGES AND LARGE-DIE PACKAGE-...
- Publication number 20160218093
- Publication date Jul 28, 2016
- Intel Corporation
- Russell K. Mortensen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
OFFSET INTERPOSERS FOR LARGE-BOTTOM PACKAGES AND LARGE-DIE PACKAGE-...
- Publication number 20160133557
- Publication date May 12, 2016
- Intel Corporation
- Russell K. Mortensen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR PACKAGE WITH EMBEDDED DIE AND ITS METHODS OF FABRICATION
- Publication number 20150050781
- Publication date Feb 19, 2015
- lintel Corporation
- John S. Guzek
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PIN GRID INTERPOSER
- Publication number 20130285242
- Publication date Oct 31, 2013
- Nicholas R. Watts
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
OFFSET INTERPOSERS FOR LARGE-BOTTOM PACKAGES AND LARGE-DIE PACKAGE-...
- Publication number 20130271907
- Publication date Oct 17, 2013
- Russell K. Mortensen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor package with embedded die and its methods of fabrication
- Publication number 20110215464
- Publication date Sep 8, 2011
- Intel Corporation
- John Stephen Guzek
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
METHOD OF EMBEDDING PASSIVE COMPONENT WITHIN VIA
- Publication number 20110198723
- Publication date Aug 18, 2011
- Todd B. Myers
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
METHOD OF STIFFENING CORELESS PACKAGE SUBSTRATE
- Publication number 20100301492
- Publication date Dec 2, 2010
- Sriram Muthukumar
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Method of stiffening coreless package substrate
- Publication number 20100207265
- Publication date Aug 19, 2010
- Sriram Muthukumar
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
SEMICONDUCTOR DEVICE WITH PACKAGE TO PACKAGE CONNECTION
- Publication number 20090321906
- Publication date Dec 31, 2009
- Nicholas Randolph Watts
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD OF EMBEDDING PASSIVE COMPONENT WITHIN VIA
- Publication number 20090057910
- Publication date Mar 5, 2009
- Intel Corporation
- Todd B. Myers
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
VIA INCLUDING MULTIPLE ELECTRICAL PATHS
- Publication number 20070117339
- Publication date May 24, 2007
- Intel Corporation
- Todd B. Myers
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Passive within via
- Publication number 20050224989
- Publication date Oct 13, 2005
- Todd B. Myers
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Via including multiple electrical paths
- Publication number 20050133918
- Publication date Jun 23, 2005
- Intel Corporation
- Todd B. Myers
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Stacked integrated circuit packages and methods of making the packages
- Publication number 20050121769
- Publication date Jun 9, 2005
- Nicholas R. Watts
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Electronic circuit housing with trench vias and method of fabricati...
- Publication number 20020071256
- Publication date Jun 13, 2002
- Intel Corporation
- David G. Figueroa
- H01 - BASIC ELECTRIC ELEMENTS

Nicholas R. Watts

Person

Patents Grantslast 30 patents

Offset interposers for large-bottom packages and large-die package-...

Offset interposers for large-bottom packages and large-die package-...

Offset interposers for large-bottom packages and large-die package-...

Offset interposers for large-bottom packages and large-die package-...

Offset interposers for large-bottom packages and large-die package-...

Passive within via

Semiconductor package with embedded die and its methods of fabrication

Pin grid interposer

Semiconductor package with embedded die and its methods of fabrication

Method of stiffening coreless package substrate

Semiconductor device with package to package connection

Method of embedding passive component within via

Method of stiffening coreless package substrate

Via including multiple electrical paths

Method of embedding passive component within via

Via including multiple electrical paths

Multilayer capacitor, wiring board, decoupling circuit, and high fr...

Electronic circuit housing with trench vias and method of fabricati...

Patents Applicationslast 30 patents

OFFSET INTERPOSERS FOR LARGE-BOTTOM PACKAGES AND LARGE-DIE PACKAGE-...

OFFSET INTERPOSERS FOR LARGE-BOTTOM PACKAGES AND LARGE-DIE PACKAGE-...

OFFSET INTERPOSERS FOR LARGE-BOTTOM PACKAGES AND LARGE-DIE PACKAGE-...

OFFSET INTERPOSERS FOR LARGE-BOTTOM PACKAGES AND LARGE-DIE PACKAGE-...

OFFSET INTERPOSERS FOR LARGE-BOTTOM PACKAGES AND LARGE-DIE PACKAGE-...

OFFSET INTERPOSERS FOR LARGE-BOTTOM PACKAGES AND LARGE-DIE PACKAGE-...

OFFSET INTERPOSERS FOR LARGE-BOTTOM PACKAGES AND LARGE-DIE PACKAGE-...

SEMICONDUCTOR PACKAGE WITH EMBEDDED DIE AND ITS METHODS OF FABRICATION

PIN GRID INTERPOSER

OFFSET INTERPOSERS FOR LARGE-BOTTOM PACKAGES AND LARGE-DIE PACKAGE-...

Semiconductor package with embedded die and its methods of fabrication

METHOD OF EMBEDDING PASSIVE COMPONENT WITHIN VIA

METHOD OF STIFFENING CORELESS PACKAGE SUBSTRATE

Method of stiffening coreless package substrate

SEMICONDUCTOR DEVICE WITH PACKAGE TO PACKAGE CONNECTION

METHOD OF EMBEDDING PASSIVE COMPONENT WITHIN VIA

VIA INCLUDING MULTIPLE ELECTRICAL PATHS

Passive within via

Via including multiple electrical paths

Stacked integrated circuit packages and methods of making the packages

Electronic circuit housing with trench vias and method of fabricati...