Nicola Telecco

Person

San Jose, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Redundancy scheme in memory
- Patent number 7,633,800
- Issue date Dec 15, 2009
- Atmel Corporation
- Vijay P. Adusumilli
- G11 - INFORMATION STORAGE
Information Patent Grant
Data register with efficient erase, program verify, and direct bit-...
- Patent number 7,580,291
- Issue date Aug 25, 2009
- Atmel Corporation
- Nicola Telecco
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Nonvolatile semiconductor memory apparatus
- Patent number 7,317,630
- Issue date Jan 8, 2008
- Atmel Corporation
- Nicola Telecco
- G11 - INFORMATION STORAGE
Information Patent Grant
Dual stage voltage regulation circuit
- Patent number 7,180,276
- Issue date Feb 20, 2007
- Atmel Corporation
- Nicola Telecco
- G05 - CONTROLLING REGULATING
Information Patent Grant
Memory architecture with enhanced over-erase tolerant control gate...
- Patent number 7,180,779
- Issue date Feb 20, 2007
- Atmel Corporation
- Nicola Telecco
- G11 - INFORMATION STORAGE
Information Patent Grant
Simultaneous external read operation during internal programming in...
- Patent number 7,159,069
- Issue date Jan 2, 2007
- Atmel Corporation
- Vijaya P. Adusumilli
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dual stage voltage regulation circuit
- Patent number 7,064,529
- Issue date Jun 20, 2006
- Atmel Corporation
- Nicola Telecco
- G05 - CONTROLLING REGULATING
Information Patent Grant
Direct memory access interface in integrated circuits
- Patent number 7,031,211
- Issue date Apr 18, 2006
- Atmel Corporation
- Nicola Telecco
- G11 - INFORMATION STORAGE
Information Patent Grant
Sense amplifier with configurable voltage swing control
- Patent number 6,700,415
- Issue date Mar 2, 2004
- Atmel Corporation
- Nicola Telecco
- G11 - INFORMATION STORAGE
Information Patent Grant
Sense amplifier with improved latching
- Patent number 6,518,798
- Issue date Feb 11, 2003
- Atmel Corporation
- Nicola Telecco
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
NOVEL ROW REDUNDANCY SCHEME IN A MULTICHIP INTEGRATED MEMORY
- Publication number 20090040825
- Publication date Feb 12, 2009
- ATMEL CORPORATION
- Vijay P. Adusumilli
- G11 - INFORMATION STORAGE
Information Patent Application
DATA REGISTER WITH EFFICIENT ERASE, PROGRAM VERIFY, AND DIRECT BIT-...
- Publication number 20080005416
- Publication date Jan 3, 2008
- ATMEL CORPORATION
- Nicola Telecco
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Nonvolatile semiconductor memory apparatus
- Publication number 20070014140
- Publication date Jan 18, 2007
- Nicola Telecco
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY ARCHITECTURE WITH ENHANCED OVER-ERASE TOLERANT CONTROL GATE...
- Publication number 20070008775
- Publication date Jan 11, 2007
- Nicola Telecco
- G11 - INFORMATION STORAGE
Information Patent Application
Dual stage voltage regulation circuit
- Publication number 20060186869
- Publication date Aug 24, 2006
- Atmel Corporation
- Nicola Telecco
- G05 - CONTROLLING REGULATING
Information Patent Application
DIRECT MEMORY ACCESS INTERFACE IN INTEGRATED CIRCUITS
- Publication number 20060077722
- Publication date Apr 13, 2006
- Nicola Telecco
- G11 - INFORMATION STORAGE
Information Patent Application
Simultaneous external read operation during internal programming in...
- Publication number 20050289314
- Publication date Dec 29, 2005
- Vijaya P. Adusumilli
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Dual stage voltage regulation circuit
- Publication number 20050057236
- Publication date Mar 17, 2005
- Nicola Telecco
- G05 - CONTROLLING REGULATING
Information Patent Application
Sense amplifier with configurable voltage swing control
- Publication number 20030025532
- Publication date Feb 6, 2003
- Nicola Telecco
- G11 - INFORMATION STORAGE
Information Patent Application
Sense amplifier with improved latching
- Publication number 20020186051
- Publication date Dec 12, 2002
- Nicola Telecco
- G11 - INFORMATION STORAGE

Nicola Telecco

Person

Patents Grantslast 30 patents

Redundancy scheme in memory

Data register with efficient erase, program verify, and direct bit-...

Nonvolatile semiconductor memory apparatus

Dual stage voltage regulation circuit

Memory architecture with enhanced over-erase tolerant control gate...

Simultaneous external read operation during internal programming in...

Dual stage voltage regulation circuit

Direct memory access interface in integrated circuits

Sense amplifier with configurable voltage swing control

Sense amplifier with improved latching

Patents Applicationslast 30 patents

NOVEL ROW REDUNDANCY SCHEME IN A MULTICHIP INTEGRATED MEMORY

DATA REGISTER WITH EFFICIENT ERASE, PROGRAM VERIFY, AND DIRECT BIT-...

Nonvolatile semiconductor memory apparatus

MEMORY ARCHITECTURE WITH ENHANCED OVER-ERASE TOLERANT CONTROL GATE...

Dual stage voltage regulation circuit

DIRECT MEMORY ACCESS INTERFACE IN INTEGRATED CIRCUITS

Simultaneous external read operation during internal programming in...

Dual stage voltage regulation circuit

Sense amplifier with configurable voltage swing control

Sense amplifier with improved latching