Nikhil Jayakumar

Person

Sunnyvale, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
High-density microbump and probe pad arrangement for semiconductor...
- Patent number 12,033,903
- Issue date Jul 9, 2024
- Amazon Technologies, Inc.
- Nikhil Jayakumar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
System and method to manage power throttling
- Patent number 11,687,136
- Issue date Jun 27, 2023
- MARVELL ASIA PTE. LTD.
- Avinash Sodani
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method to manage power throttling
- Patent number 11,340,673
- Issue date May 24, 2022
- MARVELL ASIA PTE. LTD.
- Avinash Sodani
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Approach for chip-level flop insertion and verification based on lo...
- Patent number 10,303,626
- Issue date May 28, 2019
- Cavium, LLC
- Weihuang Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Baseboard interconnection device, system and method
- Patent number 10,198,389
- Issue date Feb 5, 2019
- Cavium, LLC
- Amir H. Motamedi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Determination of flip-flop count in physical design
- Patent number 9,792,400
- Issue date Oct 17, 2017
- Cavium, Inc.
- Chirinjeev Singh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Automated flip-flop insertions in physical design without perturbat...
- Patent number 9,600,614
- Issue date Mar 21, 2017
- Xpliant
- Nikhil Jayakumar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Repeater insertions providing reduced routing perturbation caused b...
- Patent number 9,600,620
- Issue date Mar 21, 2017
- Xpliant
- Daman Ahluwalia
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System for and method of placing clock stations using variable driv...
- Patent number 9,443,053
- Issue date Sep 13, 2016
- Cavium, Inc.
- Nikhil Jayakumar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System for and method of combining CMOS inverters of multiple drive...
- Patent number 9,390,209
- Issue date Jul 12, 2016
- Cavium, Inc.
- Nikhil Jayakumar
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
System for and method of tuning clock networks constructed using va...
- Patent number 9,305,129
- Issue date Apr 5, 2016
- Cavium, Inc.
- Nikhil Jayakumar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Low power reconfigurable circuits with delay compensation
- Patent number 7,880,505
- Issue date Feb 1, 2011
- Sunil Papanchand Khatri
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
SYSTEM AND METHOD TO MANAGE POWER THROTTLING
- Publication number 20220244767
- Publication date Aug 4, 2022
- Marvell Asia Pte Ltd.
- Avinash Sodani
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
POWER MANAGEMENT AND STAGGERING TRANSITIONING FROM IDLE MODE TO OPE...
- Publication number 20210318740
- Publication date Oct 14, 2021
- Marvell Asia Pte, Ltd. (Registration No. 199702379M)
- Srinivas Sripada
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DETERMINATION OF FLIP-FLOP COUNT IN PHYSICAL DESIGN
- Publication number 20170068769
- Publication date Mar 9, 2017
- Xpliant
- Chirinjeev SINGH
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPROACH FOR CHIP-LEVEL FLOP INSERTION AND VERIFICATION BASED ON LO...
- Publication number 20160291932
- Publication date Oct 6, 2016
- Xpliant
- Weihuang WANG
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
REPEATER INSERTIONS PROVIDING REDUCED ROUTING PERTURBATION CAUSED B...
- Publication number 20160275230
- Publication date Sep 22, 2016
- Xpliant
- Daman AHLUWALIA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
AUTOMATED FLIP-FLOP INSERTIONS IN PHYSICAL DESIGN WITHOUT PERTURBAT...
- Publication number 20160224709
- Publication date Aug 4, 2016
- Xpliant
- Nikhil JAYAKUMAR
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
BASEBOARD INTERCONNECTION DEVICE, SYSTEM AND METHOD
- Publication number 20160012006
- Publication date Jan 14, 2016
- XPLIANT, INC.
- Amir H. Motamedi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
NETWORK DEVICE, SYSTEM AND METHOD HAVING A ROTATED CHIP FLOORPLAN
- Publication number 20160014885
- Publication date Jan 14, 2016
- XPLIANT, INC.
- Amir H. Motamedi
- G02 - OPTICS
Information Patent Application
SYSTEM FOR AND METHOD OF TUNING CLOCK NETWORKS CONSTRUCTED USING VA...
- Publication number 20150186583
- Publication date Jul 2, 2015
- XPLIANT, INC.
- Nikhil Jayakumar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM FOR AND METHOD OF PLACING AND ROUTING CLOCK STATIONS USING V...
- Publication number 20150186589
- Publication date Jul 2, 2015
- XPLIANT, INC.
- Nikhil Jayakumar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM FOR AND METHOD OF COMBINING CMOS INVERTERS OF MULTIPLE DRIVE...
- Publication number 20150186560
- Publication date Jul 2, 2015
- XPLIANT, INC.
- Nikhil Jayakumar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LOW POWER RECONFIGURABLE CIRCUITS WITH DELAY COMPENSATION
- Publication number 20100213978
- Publication date Aug 26, 2010
- Sunil Papanchand Khatri
- H03 - BASIC ELECTRONIC CIRCUITRY

Nikhil Jayakumar

Person

Patents Grantslast 30 patents

High-density microbump and probe pad arrangement for semiconductor...

System and method to manage power throttling

System and method to manage power throttling

Approach for chip-level flop insertion and verification based on lo...

Baseboard interconnection device, system and method

Determination of flip-flop count in physical design

Automated flip-flop insertions in physical design without perturbat...

Repeater insertions providing reduced routing perturbation caused b...

System for and method of placing clock stations using variable driv...

System for and method of combining CMOS inverters of multiple drive...

System for and method of tuning clock networks constructed using va...

Low power reconfigurable circuits with delay compensation

Patents Applicationslast 30 patents

SYSTEM AND METHOD TO MANAGE POWER THROTTLING

POWER MANAGEMENT AND STAGGERING TRANSITIONING FROM IDLE MODE TO OPE...

DETERMINATION OF FLIP-FLOP COUNT IN PHYSICAL DESIGN

APPROACH FOR CHIP-LEVEL FLOP INSERTION AND VERIFICATION BASED ON LO...

REPEATER INSERTIONS PROVIDING REDUCED ROUTING PERTURBATION CAUSED B...

AUTOMATED FLIP-FLOP INSERTIONS IN PHYSICAL DESIGN WITHOUT PERTURBAT...

BASEBOARD INTERCONNECTION DEVICE, SYSTEM AND METHOD

NETWORK DEVICE, SYSTEM AND METHOD HAVING A ROTATED CHIP FLOORPLAN

SYSTEM FOR AND METHOD OF TUNING CLOCK NETWORKS CONSTRUCTED USING VA...

SYSTEM FOR AND METHOD OF PLACING AND ROUTING CLOCK STATIONS USING V...

SYSTEM FOR AND METHOD OF COMBINING CMOS INVERTERS OF MULTIPLE DRIVE...

LOW POWER RECONFIGURABLE CIRCUITS WITH DELAY COMPENSATION