Nikhil Vishwanath Kelkar

Person

Saratoga, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Method of making a stacked inductor-electronic package
- Patent number 10,643,959
- Issue date May 5, 2020
- Intersil Americas LLC
- Zaki Moussaoui
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Method of fabricating a circuit module
- Patent number 10,582,617
- Issue date Mar 3, 2020
- Intersil Americas LLC
- Jian Yin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Power supply module with electromagnetic-interference (EMI) shieldi...
- Patent number 9,723,766
- Issue date Aug 1, 2017
- Intersil Americas LLC
- Jian Yin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Circuit module such as a high-density lead frame array (HDA) power...
- Patent number 9,717,146
- Issue date Jul 25, 2017
- Intersil Americas LLC
- Jian Yin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Packaged circuit with a lead frame and laminate substrate
- Patent number 9,613,889
- Issue date Apr 4, 2017
- Intersil Americas LLC
- Jian Yin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Stacked inductor-electronic package assembly and technique for manu...
- Patent number 9,607,917
- Issue date Mar 28, 2017
- Intersil Americas LLC
- Zaki Moussaoui
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of manufacturing a packaged circuit including a lead frame a...
- Patent number 9,012,267
- Issue date Apr 21, 2015
- Intersil Americas LLC
- Jian Yin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Package leadframe for dual side assembly
- Patent number 8,951,847
- Issue date Feb 10, 2015
- Intersil Americas LLC
- Nikhil Vishwanath Kelkar
- Y10 - TECHNICAL SUBJECTS COVERED BY FORMER USPC
Information Patent Grant
Packaged semiconductor devices including pre-molded lead-frame stru...
- Patent number 8,946,875
- Issue date Feb 3, 2015
- Intersil Americas LLC
- Nikhil Vishwanath Kelkar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods for manufacturing a radio frequency identification tag with...
- Patent number 8,635,762
- Issue date Jan 28, 2014
- National Semiconductor Corporation
- Nikhil V. Kelkar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Bond pad configurations for semiconductor dies
- Patent number 8,558,396
- Issue date Oct 15, 2013
- Intersil Americas Inc.
- Nikhil Vishwanath Kelkar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Stacked power converter structure and method
- Patent number 8,508,052
- Issue date Aug 13, 2013
- Intersil Americas Inc.
- David B. Bell
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
Information Patent Grant
Leadframe structures for semiconductor packages
- Patent number 8,445,998
- Issue date May 21, 2013
- Intersil Americas Inc.
- Young-Gon Kim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Optical sensors that reduce specular reflections
- Patent number 8,324,602
- Issue date Dec 4, 2012
- Intersil Americas Inc.
- Lynn K. Wiese
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Optical sensors that reduce specular reflections
- Patent number 8,232,541
- Issue date Jul 31, 2012
- Intersil Americas Inc.
- Lynn K. Wiese
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Tie-bar configuration for leadframe type carrier strips
- Patent number 8,206,836
- Issue date Jun 26, 2012
- Intersil Americas, Inc.
- Loyde M. Carpenter, Jr.
- Y10 - TECHNICAL SUBJECTS COVERED BY FORMER USPC
Information Patent Grant
Stacked power converter structure and method
- Patent number 7,923,300
- Issue date Apr 12, 2011
- Intersil Americas Inc.
- David B. Bell
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
Information Patent Grant
Leadframe structures for semiconductor packages
- Patent number 7,714,415
- Issue date May 11, 2010
- Intersil Americas, Inc.
- Young-Gon Kim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Solder bump formation in electronics packaging
- Patent number 7,674,702
- Issue date Mar 9, 2010
- National Semiconductor Corporation
- Viraj Patwardhan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor devices having a back surface protective coating
- Patent number 7,642,175
- Issue date Jan 5, 2010
- National Semiconductor Corporation
- Viraj A. Patwardhan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method to dispense light blocking material for wafer level CSP
- Patent number 7,510,908
- Issue date Mar 31, 2009
- National Semiconductor Corporation
- Hau Thanh Nguyen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit device package having a support coating for impr...
- Patent number 7,423,337
- Issue date Sep 9, 2008
- National Semiconductor Corporation
- Viraj A. Patwardhan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Reduced stress under bump metallization structure
- Patent number 7,420,280
- Issue date Sep 2, 2008
- National Semiconductor Corporation
- Nikhil V. Kelkar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Apparatus for forming a pre-applied underfill adhesive layer for se...
- Patent number 7,413,927
- Issue date Aug 19, 2008
- National Semiconductor Corporation
- Viraj A. Patwardhan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Solder bump formation in electronics packaging
- Patent number 7,375,431
- Issue date May 20, 2008
- National Semiconductor Corporation
- Viraj Patwardhan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Apparatus for forming a pre-applied underfill adhesive layer for se...
- Patent number 7,301,222
- Issue date Nov 27, 2007
- National Semiconductor Corporation
- Viraj A. Patwardhan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Wafer level package design that facilitates trimming and testing
- Patent number 7,282,375
- Issue date Oct 16, 2007
- National Semiconductor Corporation
- Nikhil Vishwanath Kelkar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and apparatus for forming an underfill adhesive layer
- Patent number 7,253,078
- Issue date Aug 7, 2007
- National Semiconductor Corporation
- Luu T. Nguyen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Wafer level chip scale package
- Patent number 7,241,643
- Issue date Jul 10, 2007
- National Semiconductor Corporation
- Nikhil Vishwanath Kelkar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Design of a two interconnect IC chip for a radio frequency identifi...
- Patent number 7,230,580
- Issue date Jun 12, 2007
- National Semiconductor Corporation
- Nikhil V. Kelkar
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
METHOD OF MAKING A STACKED INDUCTOR-ELECTRONIC PACKAGE
- Publication number 20200266159
- Publication date Aug 20, 2020
- INTERSIL AMERICAS LLC
- ZAKI MOUSSAOUI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CIRCUIT MODULE SUCH AS A HIGH-DENSITY LEAD FRAME ARRAY POWER MODULE...
- Publication number 20170325333
- Publication date Nov 9, 2017
- INTERSIL AMERICAS LLC
- Jian YIN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STACKED INDUCTOR-ELECTRONIC PACKAGE ASSEMBLY AND TECHNIQUE FOR MANU...
- Publication number 20170179048
- Publication date Jun 22, 2017
- INTERSIL AMERICAS LLC
- ZAKI MOUSSAOUI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PACKAGED CIRCUIT WITH A LEAD FRAME AND LAMINATE SUBSTRATE
- Publication number 20170162488
- Publication date Jun 8, 2017
- INTERSIL AMERICAS LLC
- Jian Yin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PACKAGED CIRCUIT WITH A LEAD FRAME AND LAMINATE SUBSTRATE
- Publication number 20150194370
- Publication date Jul 9, 2015
- INTERSIL AMERICAS LLC
- Jian Yin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS FOR MANUFACTURING A RADIO FREQUENCY IDENTIFICATION TAG WITH...
- Publication number 20140103120
- Publication date Apr 17, 2014
- Nikhil V. Kelkar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CIRCUIT MODULE SUCH AS A HIGH-DENSITY LEAD FRAME ARRAY (HDA) POWER...
- Publication number 20130314879
- Publication date Nov 28, 2013
- INTERSIL AMERICAS LLC
- Jian YIN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PACKAGED CIRCUIT WITH A LEAD FRAME AND LAMINATE SUBSTRATE
- Publication number 20130313694
- Publication date Nov 28, 2013
- INTERSIL AMERICAS LLC
- Jian Yin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SYSTEM AND METHODS FOR WIRE BONDING
- Publication number 20130270701
- Publication date Oct 17, 2013
- INTERSIL AMERICAS LLC
- Randolph Cruz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PACKAGED SEMICONDUCTOR DEVICES, AND RELATED METHODS AND SYSTEMS
- Publication number 20130187260
- Publication date Jul 25, 2013
- INTERSIL AMERICAS LLC
- Nikhil Vishwanath Kelkar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PACKAGE LEADFRAME FOR DUAL SIDE ASSEMBLY
- Publication number 20130181332
- Publication date Jul 18, 2013
- INTERSIL AMERICAS LLC
- Nikhil Vishwanath Kelkar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
BOND PAD CONFIGURATIONS FOR SEMICONDUCTOR DIES
- Publication number 20130015592
- Publication date Jan 17, 2013
- Intersil Americas Inc.
- Nikhil Vishwanath Kelkar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CLEAR LAYER ISOLATION
- Publication number 20120290255
- Publication date Nov 15, 2012
- Intersil Americas Inc.
- Nikhil Vishwanath Kelkar
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
HIGH-EFFICIENCY POWER CONVERTERS WITH INTEGRATED CAPACITORS
- Publication number 20120098090
- Publication date Apr 26, 2012
- Intersil Americas Inc.
- Francois Hebert
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
POWER-SUPPLY MODULE WITH ELECTROMAGNETIC-INTERFERENCE (EMI) SHIELDI...
- Publication number 20120063038
- Publication date Mar 15, 2012
- Intersil Americas Inc.
- Jian YIN
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
STACKED POWER CONVERTER STRUCTURE AND METHOD
- Publication number 20110163434
- Publication date Jul 7, 2011
- Intersil Americas Inc.
- David B. Bell
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STACKED INDUCTOR-ELECTRONIC PACKAGE ASSEMBLY AND TECHNIQUE FOR MANU...
- Publication number 20110134613
- Publication date Jun 9, 2011
- Intersil Americas Inc.
- Zaki MOUSSAOUI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Tie-Bar Configuration For Leadframe Type Carrier Strips
- Publication number 20110033724
- Publication date Feb 10, 2011
- Loyde M. Carpenter, JR.
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
LOW THERMAL RESISTANCE AND ROBUST CHIP-SCALE-PACKAGE (CSP), STRUCTU...
- Publication number 20100276701
- Publication date Nov 4, 2010
- François Hébert
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
OPTICAL SENSORS THAT REDUCE SPECTRAL REFLECTIONS
- Publication number 20100258712
- Publication date Oct 14, 2010
- Intersil Americas Inc.
- Lynn K. Wiese
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
OPTICAL SENSORS THAT REDUCE SPECTRAL REFLECTIONS
- Publication number 20100258710
- Publication date Oct 14, 2010
- Intersil Americas Inc.
- Lynn K. Wiese
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
OPTICAL SENSORS AND METHODS FOR PROVIDING OPTICAL SENSORS
- Publication number 20100259766
- Publication date Oct 14, 2010
- Intersil Americas Inc.
- Lynn K. Wiese
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Leadframe structures for semiconductor packages
- Publication number 20070252247
- Publication date Nov 1, 2007
- Young-Gon Kim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Apparatus and method for scribing semiconductor wafers using vision...
- Publication number 20030153179
- Publication date Aug 14, 2003
- National Semiconductor Corporation
- Nikhil V. Kelkar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PROCESS AND STRUCTURE IMPROVEMENTS TO SHELLCASE STYLE PACKAGING TEC...
- Publication number 20030134453
- Publication date Jul 17, 2003
- National Semiconductor Corporation
- Ashok Prabhu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method of packaging fuses
- Publication number 20010015477
- Publication date Aug 23, 2001
- Inderjit Singh
- H01 - BASIC ELECTRIC ELEMENTS

Nikhil Vishwanath Kelkar

Person

Patents Grantslast 30 patents

Method of making a stacked inductor-electronic package

Method of fabricating a circuit module

Power supply module with electromagnetic-interference (EMI) shieldi...

Circuit module such as a high-density lead frame array (HDA) power...

Packaged circuit with a lead frame and laminate substrate

Stacked inductor-electronic package assembly and technique for manu...

Method of manufacturing a packaged circuit including a lead frame a...

Package leadframe for dual side assembly

Packaged semiconductor devices including pre-molded lead-frame stru...

Methods for manufacturing a radio frequency identification tag with...

Bond pad configurations for semiconductor dies

Stacked power converter structure and method

Leadframe structures for semiconductor packages

Optical sensors that reduce specular reflections

Optical sensors that reduce specular reflections

Tie-bar configuration for leadframe type carrier strips

Stacked power converter structure and method

Leadframe structures for semiconductor packages

Solder bump formation in electronics packaging

Semiconductor devices having a back surface protective coating

Method to dispense light blocking material for wafer level CSP

Integrated circuit device package having a support coating for impr...

Reduced stress under bump metallization structure

Apparatus for forming a pre-applied underfill adhesive layer for se...

Solder bump formation in electronics packaging

Apparatus for forming a pre-applied underfill adhesive layer for se...

Wafer level package design that facilitates trimming and testing

Method and apparatus for forming an underfill adhesive layer

Wafer level chip scale package

Design of a two interconnect IC chip for a radio frequency identifi...

Patents Applicationslast 30 patents

METHOD OF MAKING A STACKED INDUCTOR-ELECTRONIC PACKAGE

CIRCUIT MODULE SUCH AS A HIGH-DENSITY LEAD FRAME ARRAY POWER MODULE...

STACKED INDUCTOR-ELECTRONIC PACKAGE ASSEMBLY AND TECHNIQUE FOR MANU...

PACKAGED CIRCUIT WITH A LEAD FRAME AND LAMINATE SUBSTRATE

PACKAGED CIRCUIT WITH A LEAD FRAME AND LAMINATE SUBSTRATE

METHODS FOR MANUFACTURING A RADIO FREQUENCY IDENTIFICATION TAG WITH...

CIRCUIT MODULE SUCH AS A HIGH-DENSITY LEAD FRAME ARRAY (HDA) POWER...

PACKAGED CIRCUIT WITH A LEAD FRAME AND LAMINATE SUBSTRATE

SYSTEM AND METHODS FOR WIRE BONDING

PACKAGED SEMICONDUCTOR DEVICES, AND RELATED METHODS AND SYSTEMS

PACKAGE LEADFRAME FOR DUAL SIDE ASSEMBLY

BOND PAD CONFIGURATIONS FOR SEMICONDUCTOR DIES

CLEAR LAYER ISOLATION

HIGH-EFFICIENCY POWER CONVERTERS WITH INTEGRATED CAPACITORS

POWER-SUPPLY MODULE WITH ELECTROMAGNETIC-INTERFERENCE (EMI) SHIELDI...

STACKED POWER CONVERTER STRUCTURE AND METHOD

STACKED INDUCTOR-ELECTRONIC PACKAGE ASSEMBLY AND TECHNIQUE FOR MANU...

Tie-Bar Configuration For Leadframe Type Carrier Strips

LOW THERMAL RESISTANCE AND ROBUST CHIP-SCALE-PACKAGE (CSP), STRUCTU...

OPTICAL SENSORS THAT REDUCE SPECTRAL REFLECTIONS

OPTICAL SENSORS THAT REDUCE SPECTRAL REFLECTIONS

OPTICAL SENSORS AND METHODS FOR PROVIDING OPTICAL SENSORS

Leadframe structures for semiconductor packages

Apparatus and method for scribing semiconductor wafers using vision...

PROCESS AND STRUCTURE IMPROVEMENTS TO SHELLCASE STYLE PACKAGING TEC...

Method of packaging fuses