Understanding that the drawings depict only exemplary embodiments and are not therefore to be considered limiting in scope, the exemplary embodiments will be described with additional specificity and detail through the use of the accompanying drawings, in which:
In accordance with common practice, the various described features are not drawn to scale but are drawn to emphasize specific features relevant to the exemplary embodiments.
In the following detailed description, reference is made to the accompanying drawings that form a part hereof, and in which is shown by way of illustration specific illustrative embodiments. It is to be understood that other embodiments may be utilized and that mechanical and electrical changes may be made. The following detailed description is, therefore, not to be taken in a limiting sense.
High-efficiency power converters with integrated capacitors are disclosed herein. The present power converters utilize a chip capacitor having an integrated circuit compatible planar structure that is thin and compatible with standard package outlines. The chip capacitor is stacked over a single power die. The power die includes highs side and low side power devices that are monolithically integrated in a single die, with the phase (switched output) node at the bottom of the die. The top of the high-side device is the voltage input (Vin) and the top of the low-side device is ground.
The chip capacitor is mounted over the top of the power die in a stacked configuration prior to packaging. In some embodiments, the capacitor can be mounted by flip-chip bonding to the power die, or by flip-chip bonding on a metal plate that is coupled to the power die. In other embodiments, the capacitor is mounted to the power die by wire bonding. The components of the power converter are encapsulated in a molding package material such that the capacitor does not extend outside of the molded package.
The capacitor can be implemented with a capacitance value selected to minimize power loss of the power converter. In the present approach, the distance between a critical node and the capacitor is reduced, resulting in a parasitic inductance reduced to an acceptable level between the capacitor electrodes and the voltage input (Vin) and ground nodes. The present approach is particularly suitable for direct current (DC)-to-DC synchronous power converters.
The present power converters, which can have one or more integrated capacitors, can be optionally combined in a package with an integrated circuit (IC) to produce a “stand alone” power converter or regulator product. The IC can be a full featured switching modulator and converter, which generates a pulse-width modulation (PWM) signal, drives the gates of the metal oxide semiconductor field effect transistors (MOSFETs) in the power die, has over current and over voltage protection, and the like. The IC die can also be a gate driver, which takes a single PWM signal and drives the gates of the MOSFETs in the power die, a switching regulator circuit, or the like.
In the embodiments described as follows, the power converters with integrated capacitors include a power die, and an IC die that is optional. Thus, the various embodiments of the power converter described hereafter with reference to the drawings can be implemented with or without the IC die as desired.
A pair of metal plates 110 is coupled to power die 102 and outer portions of lead frame 106 with conductive die attach pads 108b. The metal plates 110 each include a raised portion 111 that is coupled to power die 102, and provide one or more conductive paths between power die 102 and lead frame 106. The metal plates 110 can be made of copper, copper alloys, multi-layer structures such as Cu/Mo/Cu, and the like.
A capacitor die 112 is mounted on metal plates 110 by flip-chip bonding such as with a conductive die attach pads 108c. The capacitor die 112 is attached to each raised portion 111 of metal plates 110 over power die 102.
A plurality of bond pads 114 are located on an upper surface 116 of power die 102. A plurality of bond pads 118 are located on an upper surface 120 of IC die 104. The bond pads 114 are electrically connected to respective bond pads 118 by bond wires 122, which provide power signals from power die 102 to IC die 104. Other bond pads 118 are electrically connected to various outer portions of lead frame 106 by bond wires 124 to provide outside connections for IC die 104.
A packaging material 126, such as a polymer molding compound, encapsulates the various components of power converter 100, including power die 102, IC die 104, and capacitor die 112, to seal the components from environmental contamination. Exemplary packaging materials include molding compounds formed of various resins including aromatic or multi-aromatic resins, phenolic resins, and the like, which can include a filler material such as silica or other materials. For example, improved electro magnetic interference (EMI) shielding can be obtained by adding ferrite powder as a filler material to the resin.
In one embodiment of the power die, a high-side device and a low-side device, which are required in DC-DC synchronous power converters, are integrated on the same die. The power die is configured with the switched node (phase node or output) at the bottom of the die.
In one embodiment, the capacitor die can be implemented as a textured capacitor such as a trenched capacitor. For example, a trench-gate capacitor can be implemented in the substrate of the stacked capacitor to increase the area. The capacitance per unit area can be increased significantly, without impacting the voltage rating, by using trenched capacitors. In another embodiment, the capacitor die has substantially planar structures. For example, a nitride layer can be deposited on a thin oxide layer to form reliable planar capacitor structures.
The layers of the capacitor die can be formed by various conventional deposition techniques, such as atomic layer deposition (ALD), low pressure chemical vapor deposition (CVD), metal organic CVD, plasma vapor deposition (PVD) sputtering, and the like.
The dielectric layers of the capacitor die can be formed with various dielectric materials, which can have dielectric constants well in excess of an oxide. For example, a high dielectric constant material, such as barium strontium titanate (BaSrTiO3), lead zirconium titanate (Pb(ZR1-xTi)O3), strontium titanate (SrTiO3) or tantalum oxide (Ta2O5) can be utilized. These materials provide a dielectric constant greater than about 100. Other suitable dielectric materials include hafnium silicate, zirconium silicate, zirconium dioxide, aluminum oxide, and the like.
The foregoing details related to the power die and capacitor are applicable to the additional embodiments of the power converter described as follows.
A capacitor die 412 is mounted on metal plates 410 by flip-chip bonding with one or more solder balls 413. The capacitor die 412 is attached to each raised portion 411 of metal plates 110 over power die 102.
A plurality of bond pads 414 are located on an upper surface 416 of power die 402. A plurality of bond pads 418 are located on an upper surface 420 of IC die 404. The bond pads 414 are electrically connected to respective bond pads 418 by bond wires 422, which provide power signals from power die 402 to IC die 404. Other bond pads 418 are electrically connected to various outer portions of lead frame 406 by bond wires 424 to provide outside connections for IC die 404.
A packaging material 426, such as a polymer molding compound, encapsulates the various components of power converter 400, including power die 402, IC die 404, and capacitor die 412, to seal the components from environmental contamination.
A plurality of bond pads 514 are located on upper surface 503 of power die 502. A plurality of bond pads 518 are located on an upper surface 520 of IC die 504. The bond pads 514 are electrically connected to respective bond pads 518 by bond wires 522, which provide power signals from power die 502 to IC die 504. Other bond pads 518 are electrically connected to various outer portions of lead frame 506 by bond wires 524 to provide outside connections for IC die 504. A packaging material 526 encapsulates the various components of power converter 500, including power die 502, IC die 504, and capacitor die 512.
A plurality of bond pads 614 are located on upper surface 603 of power die 602. A plurality of bond pads 618 are located on an upper surface 620 of IC die 604. The bond pads 614 are electrically connected to respective bond pads 618 by bond wires 622, which provide power signals from power die 602 to IC die 604. Other bond pads 618 are electrically connected to various outer portions of lead frame 606 by bond wires 624 to provide outside connections for IC die 604. A packaging material 626 encapsulates the various components of power converter 600, including power die 602, IC die 604, and capacitor die 612.
A capacitor die 716 is mounted between raised section 713 and raised section 714 over power die 702. The capacitor die 716 has a top contact 717 and a bottom contact 718. The top contact 717 is coupled to raised section 714, and bottom contact 718 is coupled to raised section 713.
A plurality of bond pads 720 is located on upper surface 703 of power die 702. A plurality of bond pads 724 is located on an upper surface 726 of IC die 704. The bond pads 720 are electrically connected to respective bond pads 724 by bond wires 728, which provide power signals from power die 702 to IC die 704. Other bond pads 724 are electrically connected to various outer portions of lead frame 706 by bond wires 730 to provide outside connections for IC die 704.
A packaging material 732, such as a polymer molding compound, encapsulates the various components of power converter 700, including power die 702, IC die 704, and capacitor die 716, to seal the components from environmental contamination. A bottom portion 709 of lead frame 706 is exposed through packaging material 732 to the outside environment. The bottom portion 709 provides for electrical connections to the bottom of power die 702, and direct heat sinking to the outside environment.
A second metal plate 811 is coupled to power die 802 and outer portions of lead frame 806 with conductive die attach pads 812. The first metal plate 810 has a raised section 813 that extends over a portion of power die 802. The second metal plate 811 has a raised section 814 that extends over a portion of power die 802 and over a portion of raised section 813.
A capacitor die 816 is mounted between raised section 813 and raised section 814 over power die 802. The capacitor die 816 has a top contact 817 and a bottom contact 818. The top contact 817 is coupled to raised section 814, and bottom contact 818 is coupled to raised section 813.
A plurality of bond pads 820 is located on upper surface 803 of power die 802. A plurality of bond pads 824 is located on an upper surface 826 of IC die 804. The bond pads 820 are electrically connected to respective bond pads 824 by bond wires 828, which provide power signals from power die 802 to IC die 804. Other bond pads 824 are electrically connected to various outer portions of lead frame 806 by bond wires 830 to provide outside connections for IC die 804.
A packaging material 832 encapsulates the various components of power converter 800, including power die 802, IC die 804, and capacitor die 816, to seal the components. A bottom portion 809 of lead frame 806 is exposed through packaging material 832 to the outside environment. The bottom portion 809 provides for electrical connections to the bottom of power die 802, and direct heat sinking to the outside environment.
As shown in
The calculated capacitances of various capacitors are set forth in Tables 1 and 2. Table 1 lists the calculated capacitances for capacitors with varying thicknesses of oxide/nitride planar capacitor structures. Table 2 shows that capacitances greater than 1 micro-Farad are feasible when the capacitors are based on dielectric materials with a higher dielectric constant than oxide/nitride. The BV in Table 2 and the BVox in Table 1 are the estimated breakdown voltage of the dielectric or dielectric stack. Typically, the maximum electric field at breakdown is around 9 MeV/cm. The Operating Voltage column in Table 1 is simply ⅓ of the BVox value.
Computer simulations using published transistor models were carried out in order to evaluate the impact of an integrated capacitor on circuit performance. The results of the simulations are shown in the graphs of
The computer simulations showed that adding capacitance reduces total power loss by about 10% and also reduces ringing. Also, by fine tuning the capacitance for the application (depending on inductance, etc.), up to about 20% reduction in power loss can be achieved.
Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that any arrangement, which is calculated to achieve the same purpose, may be substituted for the specific embodiments shown. Therefore, it is manifestly intended that this invention be limited only by the claims and the equivalents thereof.
This application claims the benefit of priority to U.S. Provisional Application No. 61/421,280, filed on Dec. 9, 2010, and to U.S. Provisional Application No. 61/405,931, filed on Oct. 22, 2010, the disclosures of which are incorporated by reference.
Number | Date | Country | |
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61405931 | Oct 2010 | US | |
61421280 | Dec 2010 | US |