Niranjan Kulkarni

Person

Phoenix, AZ, US

People

Patents Grantslast 30 patents

Information Patent Grant
Clock skewing strategy to reduce dynamic power and eliminate hold-t...
- Patent number 10,551,869
- Issue date Feb 4, 2020
- Arizona Board of Regents on behalf of Arizona State University
- Sarma Vrudhula
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hold violation free scan chain and scanning mechanism for testing o...
- Patent number 10,447,249
- Issue date Oct 15, 2019
- Arizona Board of Regents on behalf of Arizona State University
- Sarma Vrudhula
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Energy efficient, robust differential mode d-flip-flop
- Patent number 10,250,236
- Issue date Apr 2, 2019
- Arizona Board of Regents on behalf of Arizona State University
- Sarma Vrudhula
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method of obfuscating digital logic circuits using threshold voltage
- Patent number 9,876,503
- Issue date Jan 23, 2018
- Arixona Board of Regents on Behalf of Arizona State University
- Sarma Vrudhula
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Robust, low power, reconfigurable threshold logic array
- Patent number 9,490,815
- Issue date Nov 8, 2016
- Arizona Board of Regents on behalf of Arizona State University
- Sarma Vrudhula
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Threshold logic element with stabilizing feedback
- Patent number 9,473,139
- Issue date Oct 18, 2016
- Arizona Board of Regents on behalf of Arizona State University
- Sarma Vrudhula
- G11 - INFORMATION STORAGE
Information Patent Grant
Threshold logic gates with resistive networks
- Patent number 9,356,598
- Issue date May 31, 2016
- Arizona Board of Regents on behalf of Arizona State University
- Sarma Vrudhula
- G11 - INFORMATION STORAGE
Information Patent Grant
Threshold gate and threshold logic array
- Patent number 9,306,151
- Issue date Apr 5, 2016
- Arizona Board of Regents, a body corporate of the State of Arizona, acting fo...
- Sarma Vrudhula
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Technology mapping for threshold and logic gate hybrid circuits
- Patent number 8,832,614
- Issue date Sep 9, 2014
- Arizona Board of Regents, a body corporate of the State of Arizona, acting fo...
- Sarma Vrudhula
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
ENERGY EFFICIENT, ROBUST DIFFERENTIAL MODE D-FLIP-FLOP
- Publication number 20180159512
- Publication date Jun 7, 2018
- Arizona Board of Regents on behalf of Arizona State University
- Sarma Vrudhula
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
HOLD VIOLATION FREE SCAN CHAIN AND SCANNING MECHANISM FOR TESTING O...
- Publication number 20180102766
- Publication date Apr 12, 2018
- Arizona Board of Regents on behalf of Arizona State University
- Sarma Vrudhula
- G01 - MEASURING TESTING
Information Patent Application
CLOCK SKEWING STRATEGY TO REDUCE DYNAMIC POWER AND ELIMINATE HOLD-T...
- Publication number 20170248989
- Publication date Aug 31, 2017
- Arizona Board of Regents on behalf of Arizona State University
- Sarma Vrudhula
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD OF OBFUSCATING DIGITAL LOGIC CIRCUITS USING THRESHOLD VOLTAGE
- Publication number 20170187382
- Publication date Jun 29, 2017
- Arizona Board of Regents on behalf of Arizona State University
- Sarma Vrudhula
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
ROBUST, LOW POWER, RECONFIGURABLE THRESHOLD LOGIC ARRAY
- Publication number 20160164526
- Publication date Jun 9, 2016
- Arizona Board of Regents on behalf of Arizona State University
- Sarma Vrudhula
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
THRESHOLD LOGIC ELEMENT WITH STABILIZING FEEDBACK
- Publication number 20160006438
- Publication date Jan 7, 2016
- Arizona Board of Regents on behalf of Arizona State University
- Sarma Vrudhula
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
THRESHOLD LOGIC GATES WITH RESISTIVE NETWORKS
- Publication number 20160006437
- Publication date Jan 7, 2016
- Arizona Board of Regents on behalf of Arizona State University
- Sarma Vrudhula
- G11 - INFORMATION STORAGE
Information Patent Application
TECHNOLOGY MAPPING FOR THRESHOLD AND LOGIC GATE HYBRID CIRCUITS
- Publication number 20130339914
- Publication date Dec 19, 2013
- Arizona Board of Regents, a body Corporate of the State of Arizona, Acting fo...
- Sarma Vrudhula
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
THRESHOLD GATE AND THRESHOLD LOGIC ARRAY
- Publication number 20130313623
- Publication date Nov 28, 2013
- Arizona Board of Regents, a body Corporate of the State of Arizona, Acting fo...
- Sarma Vrudhula
- H01 - BASIC ELECTRIC ELEMENTS

Niranjan Kulkarni

Person

Patents Grantslast 30 patents

Clock skewing strategy to reduce dynamic power and eliminate hold-t...

Hold violation free scan chain and scanning mechanism for testing o...

Energy efficient, robust differential mode d-flip-flop

Method of obfuscating digital logic circuits using threshold voltage

Robust, low power, reconfigurable threshold logic array

Threshold logic element with stabilizing feedback

Threshold logic gates with resistive networks

Threshold gate and threshold logic array

Technology mapping for threshold and logic gate hybrid circuits

Patents Applicationslast 30 patents

ENERGY EFFICIENT, ROBUST DIFFERENTIAL MODE D-FLIP-FLOP

HOLD VIOLATION FREE SCAN CHAIN AND SCANNING MECHANISM FOR TESTING O...

CLOCK SKEWING STRATEGY TO REDUCE DYNAMIC POWER AND ELIMINATE HOLD-T...

METHOD OF OBFUSCATING DIGITAL LOGIC CIRCUITS USING THRESHOLD VOLTAGE

ROBUST, LOW POWER, RECONFIGURABLE THRESHOLD LOGIC ARRAY

THRESHOLD LOGIC ELEMENT WITH STABILIZING FEEDBACK

THRESHOLD LOGIC GATES WITH RESISTIVE NETWORKS

TECHNOLOGY MAPPING FOR THRESHOLD AND LOGIC GATE HYBRID CIRCUITS

THRESHOLD GATE AND THRESHOLD LOGIC ARRAY