Nitin Chawla

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Patents Grantslast 30 patents

Information Patent Grant
Adaptive bit line overdrive control for an in-memory compute operat...
- Patent number 11,984,151
- Issue date May 14, 2024
- STMICROELECTRONICS INTERNATIONAL N.V.
- Harsh Rawat
- G11 - INFORMATION STORAGE
Information Patent Grant
Variable clock adaptation in neural network processors
- Patent number 11,900,240
- Issue date Feb 13, 2024
- STMicroelectronics S.r.l.
- Nitin Chawla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Tagged memory operated at lower vmin in error tolerant system
- Patent number 11,836,346
- Issue date Dec 5, 2023
- STMicroelectronics S.r.l.
- Nitin Chawla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Elements for in-memory compute
- Patent number 11,829,730
- Issue date Nov 28, 2023
- STMicroelectronics S.r.l.
- Nitin Chawla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Streaming access memory device, system and method
- Patent number 11,823,771
- Issue date Nov 21, 2023
- STMicroelectronics S.r.l.
- Nitin Chawla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory management device, system and method
- Patent number 11,749,343
- Issue date Sep 5, 2023
- STMICROELECTRONICS INTERNATIONAL N.V.
- Nitin Chawla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Computing system power management device, system and method
- Patent number 11,726,543
- Issue date Aug 15, 2023
- STMicroelectronics S.r.l.
- Nitin Chawla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
In-memory compute array with integrated bias elements
- Patent number 11,605,424
- Issue date Mar 14, 2023
- STMICROELECTRONICS INTERNATIONAL N.V.
- Anuj Grover
- G11 - INFORMATION STORAGE
Information Patent Grant
Elements for in-memory compute
- Patent number 11,474,788
- Issue date Oct 18, 2022
- STMicroelectronics S.r.l.
- Nitin Chawla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Tagged memory operated at lower vmin in error tolerant system
- Patent number 11,360,667
- Issue date Jun 14, 2022
- STMicroelectronics S.r.l.
- Nitin Chawla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory management device, system and method
- Patent number 11,257,543
- Issue date Feb 22, 2022
- STMICROELECTRONICS INTERNATIONAL N.V.
- Nitin Chawla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
In-memory compute array with integrated bias elements
- Patent number 11,094,376
- Issue date Aug 17, 2021
- STMICROELECTRONICS INTERNATIONAL N.V.
- Anuj Grover
- G11 - INFORMATION STORAGE
Information Patent Grant
Calibration arrangement
- Patent number 9,021,324
- Issue date Apr 28, 2015
- STMicroelectronics International N.V.
- Nitin Chawla
- G11 - INFORMATION STORAGE
Information Patent Grant
Adaptive multi-stage slack borrowing for high performance error res...
- Patent number 8,994,416
- Issue date Mar 31, 2015
- STMicroelectronics International N.V.
- Chittoor Parthasarathy
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Adaptive multi-stage slack borrowing for high performance error res...
- Patent number 8,552,765
- Issue date Oct 8, 2013
- STMicroelectronics International N.V.
- Chittoor Parthasarathy
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Fail safe adaptive voltage/frequency system
- Patent number 8,269,545
- Issue date Sep 18, 2012
- STMicroelectronics International N.V.
- Nitin Chawla
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Fail safe adaptive voltage/frequency system
- Patent number 8,154,335
- Issue date Apr 10, 2012
- STMicroelectronics Pvt. Ltd.
- Nitin Chawla
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Spread spectrum clock generation
- Patent number 8,037,336
- Issue date Oct 11, 2011
- STMicroelectronics PVT, Ltd.
- Nitin Chawla
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Device for implementing a sum of products expression
- Patent number 7,917,569
- Issue date Mar 29, 2011
- STMicroelectronics Pvt. Ltd.
- Aditya Bhuvanagiri
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Minimal area integrated circuit implementation of a polyphase inter...
- Patent number 7,698,355
- Issue date Apr 13, 2010
- STMicroelectronics Pvt. Ltd.
- Aditya Bhuvanagiri
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
BIT LINE ACCUMULATION READOUT SCHEME FOR AN ANALOG IN-MEMORY COMPUT...
- Publication number 20240177769
- Publication date May 30, 2024
- STMicroelectronics International N.V.
- Promod KUMAR
- G11 - INFORMATION STORAGE
Information Patent Application
TUNING OF READ/WRITE CYCLE TIME DELAY FOR A MEMORY CIRCUIT DEPENDEN...
- Publication number 20240143239
- Publication date May 2, 2024
- STMicroelectronics International N.V.
- Bhupender SINGH
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
AT-SPEED TRANSITION FAULT TESTING FOR A MULTI-PORT AND MULTI-CLOCK...
- Publication number 20240112748
- Publication date Apr 4, 2024
- STMicroelectronics International N.V.
- Tanuj KUMAR
- G11 - INFORMATION STORAGE
Information Patent Application
ANALOG IN-MEMORY COMPUTATION PROCESSING CIRCUIT USING SEGMENTED MEM...
- Publication number 20240112728
- Publication date Apr 4, 2024
- STMicroelectronics International N.V.
- Harsh RAWAT
- G11 - INFORMATION STORAGE
Information Patent Application
BUILT-IN SELF TEST CIRCUIT FOR SEGMENTED STATIC RANDOM ACCESS MEMOR...
- Publication number 20240069096
- Publication date Feb 29, 2024
- STMicroelectronics International N.V.
- Bhupender SINGH
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY ARCHITECTURE SUPPORTING BOTH CONVENTIONAL MEMORY ACCESS MODE...
- Publication number 20240071429
- Publication date Feb 29, 2024
- STMicroelectronics International N.V.
- Harsh RAWAT
- G11 - INFORMATION STORAGE
Information Patent Application
BUILT-IN SELF TEST CIRCUIT FOR SEGMENTED STATIC RANDOM ACCESS MEMOR...
- Publication number 20240071546
- Publication date Feb 29, 2024
- STMicroelectronics International N.V.
- Hitesh CHAWLA
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY ARCHITECTURE SUPPORTING BOTH CONVENTIONAL MEMORY ACCESS MODE...
- Publication number 20240071439
- Publication date Feb 29, 2024
- STMicroelectronics International N.V.
- Harsh RAWAT
- G11 - INFORMATION STORAGE
Information Patent Application
TAGGED MEMORY OPERATED AT LOWER VMIN IN ERROR TOLERANT SYSTEM
- Publication number 20240045589
- Publication date Feb 8, 2024
- STMicroelectronics S.r.l.
- Nitin CHAWLA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
BIT LINE READ CURRENT MIRRORING CIRCUIT FOR AN IN-MEMORY COMPUTE OP...
- Publication number 20230410892
- Publication date Dec 21, 2023
- STMicroelectronics International N.V.
- Kedar Janardan DHORI
- G11 - INFORMATION STORAGE
Information Patent Application
IN-MEMORY COMPUTATION CIRCUIT USING STATIC RANDOM ACCESS MEMORY (SR...
- Publication number 20230410862
- Publication date Dec 21, 2023
- STMicroelectronics International N.V.
- Harsh RAWAT
- G11 - INFORMATION STORAGE
Information Patent Application
BIT LINE VOLTAGE CLAMPING READ CIRCUIT FOR AN IN-MEMORY COMPUTE OPE...
- Publication number 20230386566
- Publication date Nov 30, 2023
- STMicroelectronics International N.V.
- Kedar Janardan DHORI
- G11 - INFORMATION STORAGE
Information Patent Application
IN-MEMORY COMPUTATION CIRCUIT USING STATIC RANDOM ACCESS MEMORY (SR...
- Publication number 20230386565
- Publication date Nov 30, 2023
- STMicroelectronics International N.V.
- Kedar Janardan DHORI
- G11 - INFORMATION STORAGE
Information Patent Application
ENHANCED ACCURACY OF BIT LINE READING FOR AN IN-MEMORY COMPUTE OPER...
- Publication number 20230386564
- Publication date Nov 30, 2023
- STMicroelectronics International N.V.
- Kedar Janardan DHORI
- G11 - INFORMATION STORAGE
Information Patent Application
COMPUTING SYSTEM POWER MANAGEMENT DEVICE, SYSTEM AND METHOD
- Publication number 20230350483
- Publication date Nov 2, 2023
- STMicroelectronics S.r.l.
- Nitin CHAWLA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
IN-MEMORY COMPUTE ARRAY WITH INTEGRATED BIAS ELEMENTS
- Publication number 20230186983
- Publication date Jun 15, 2023
- STMicroelectronics International N.V.
- Anuj GROVER
- G11 - INFORMATION STORAGE
Information Patent Application
BIT-CELL ARCHITECTURE BASED IN-MEMORY COMPUTE
- Publication number 20230102492
- Publication date Mar 30, 2023
- STMicroelectronics International N.V.
- Harsh RAWAT
- G11 - INFORMATION STORAGE
Information Patent Application
ADAPTIVE BODY BIAS MANAGEMENT FOR AN IN-MEMORY COMPUTE OPERATION WH...
- Publication number 20230012567
- Publication date Jan 19, 2023
- STMicroelectronics International N.V.
- Harsh RAWAT
- G11 - INFORMATION STORAGE
Information Patent Application
ADAPTIVE BIT LINE OVERDRIVE CONTROL FOR AN IN-MEMORY COMPUTE OPERAT...
- Publication number 20230009329
- Publication date Jan 12, 2023
- STMicroelectronics International N.V.
- Harsh RAWAT
- G11 - INFORMATION STORAGE
Information Patent Application
SERIAL WORD LINE ACTUATION WITH LINKED SOURCE VOLTAGE SUPPLY MODULA...
- Publication number 20230008833
- Publication date Jan 12, 2023
- STMicroelectronics International N.V.
- Harsh RAWAT
- G11 - INFORMATION STORAGE
Information Patent Application
SELECTIVE BIT LINE CLAMPING CONTROL FOR AN IN-MEMORY COMPUTE OPERAT...
- Publication number 20230012303
- Publication date Jan 12, 2023
- STMicroelectronics International N.V.
- Kedar Janardan DHORI
- G11 - INFORMATION STORAGE
Information Patent Application
ADAPTIVE WORD LINE UNDERDRIVE CONTROL FOR AN IN-MEMORY COMPUTE OPER...
- Publication number 20230008275
- Publication date Jan 12, 2023
- STMicroelectronics International N.V.
- Kedar Janardan DHORI
- G11 - INFORMATION STORAGE
Information Patent Application
ELEMENTS FOR IN-MEMORY COMPUTE
- Publication number 20230004354
- Publication date Jan 5, 2023
- STMicroelectronics S.r.l.
- Nitin CHAWLA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TAGGED MEMORY OPERATED AT LOWER VMIN IN ERROR TOLERANT SYSTEM
- Publication number 20220269410
- Publication date Aug 25, 2022
- STMicroelectronics S.r.l.
- Nitin CHAWLA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY MANAGEMENT DEVICE, SYSTEM AND METHOD
- Publication number 20220139453
- Publication date May 5, 2022
- STMicroelectronics International N.V.
- Nitin CHAWLA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
IN-MEMORY COMPUTE ARRAY WITH INTEGRATED BIAS ELEMENTS
- Publication number 20210343334
- Publication date Nov 4, 2021
- STMicroelectronics International N.V.
- Anuj GROVER
- G11 - INFORMATION STORAGE
Information Patent Application
STREAMING ACCESS MEMORY DEVICE, SYSTEM AND METHOD
- Publication number 20210241806
- Publication date Aug 5, 2021
- STMicroelectronics International N.V.
- Nitin CHAWLA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COMPUTING SYSTEM POWER MANAGEMENT DEVICE, SYSTEM AND METHOD
- Publication number 20210181828
- Publication date Jun 17, 2021
- STMicroelectronics S.r.l.
- Nitin CHAWLA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
VARIABLE CLOCK ADAPTATION IN NEURAL NETWORK PROCESSORS
- Publication number 20210081773
- Publication date Mar 18, 2021
- STMicroelectronics S.r.l.
- Nitin CHAWLA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TAGGED MEMORY OPERATED AT LOWER VMIN IN ERROR TOLERANT SYSTEM
- Publication number 20210072894
- Publication date Mar 11, 2021
- STMicroelectronics S.r.l.
- Nitin CHAWLA
- G06 - COMPUTING CALCULATING COUNTING

Nitin Chawla

Person

Patents Grantslast 30 patents

Adaptive bit line overdrive control for an in-memory compute operat...

Variable clock adaptation in neural network processors

Tagged memory operated at lower vmin in error tolerant system

Elements for in-memory compute

Streaming access memory device, system and method

Memory management device, system and method

Computing system power management device, system and method

In-memory compute array with integrated bias elements

Elements for in-memory compute

Tagged memory operated at lower vmin in error tolerant system

Memory management device, system and method

In-memory compute array with integrated bias elements

Calibration arrangement

Adaptive multi-stage slack borrowing for high performance error res...

Adaptive multi-stage slack borrowing for high performance error res...

Fail safe adaptive voltage/frequency system

Fail safe adaptive voltage/frequency system

Spread spectrum clock generation

Device for implementing a sum of products expression

Minimal area integrated circuit implementation of a polyphase inter...

Patents Applicationslast 30 patents

BIT LINE ACCUMULATION READOUT SCHEME FOR AN ANALOG IN-MEMORY COMPUT...

TUNING OF READ/WRITE CYCLE TIME DELAY FOR A MEMORY CIRCUIT DEPENDEN...

AT-SPEED TRANSITION FAULT TESTING FOR A MULTI-PORT AND MULTI-CLOCK...

ANALOG IN-MEMORY COMPUTATION PROCESSING CIRCUIT USING SEGMENTED MEM...

BUILT-IN SELF TEST CIRCUIT FOR SEGMENTED STATIC RANDOM ACCESS MEMOR...

MEMORY ARCHITECTURE SUPPORTING BOTH CONVENTIONAL MEMORY ACCESS MODE...

BUILT-IN SELF TEST CIRCUIT FOR SEGMENTED STATIC RANDOM ACCESS MEMOR...

MEMORY ARCHITECTURE SUPPORTING BOTH CONVENTIONAL MEMORY ACCESS MODE...

TAGGED MEMORY OPERATED AT LOWER VMIN IN ERROR TOLERANT SYSTEM

BIT LINE READ CURRENT MIRRORING CIRCUIT FOR AN IN-MEMORY COMPUTE OP...

IN-MEMORY COMPUTATION CIRCUIT USING STATIC RANDOM ACCESS MEMORY (SR...

BIT LINE VOLTAGE CLAMPING READ CIRCUIT FOR AN IN-MEMORY COMPUTE OPE...

IN-MEMORY COMPUTATION CIRCUIT USING STATIC RANDOM ACCESS MEMORY (SR...

ENHANCED ACCURACY OF BIT LINE READING FOR AN IN-MEMORY COMPUTE OPER...

COMPUTING SYSTEM POWER MANAGEMENT DEVICE, SYSTEM AND METHOD

IN-MEMORY COMPUTE ARRAY WITH INTEGRATED BIAS ELEMENTS

BIT-CELL ARCHITECTURE BASED IN-MEMORY COMPUTE

ADAPTIVE BODY BIAS MANAGEMENT FOR AN IN-MEMORY COMPUTE OPERATION WH...

ADAPTIVE BIT LINE OVERDRIVE CONTROL FOR AN IN-MEMORY COMPUTE OPERAT...

SERIAL WORD LINE ACTUATION WITH LINKED SOURCE VOLTAGE SUPPLY MODULA...

SELECTIVE BIT LINE CLAMPING CONTROL FOR AN IN-MEMORY COMPUTE OPERAT...

ADAPTIVE WORD LINE UNDERDRIVE CONTROL FOR AN IN-MEMORY COMPUTE OPER...

ELEMENTS FOR IN-MEMORY COMPUTE

TAGGED MEMORY OPERATED AT LOWER VMIN IN ERROR TOLERANT SYSTEM

MEMORY MANAGEMENT DEVICE, SYSTEM AND METHOD

IN-MEMORY COMPUTE ARRAY WITH INTEGRATED BIAS ELEMENTS

STREAMING ACCESS MEMORY DEVICE, SYSTEM AND METHOD

COMPUTING SYSTEM POWER MANAGEMENT DEVICE, SYSTEM AND METHOD

VARIABLE CLOCK ADAPTATION IN NEURAL NETWORK PROCESSORS

TAGGED MEMORY OPERATED AT LOWER VMIN IN ERROR TOLERANT SYSTEM