Om P. Agrawal

Person

Los Altos, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Clock distribution chip
- Patent number 8,122,277
- Issue date Feb 21, 2012
- Lattice Semiconductor Corporation
- Shyam Chandra
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Clock distribution chip
- Patent number 8,112,656
- Issue date Feb 7, 2012
- Lattice Semiconductor Corporation
- Shyam Chandra
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Flexible memory architectures for programmable logic devices
- Patent number 7,957,208
- Issue date Jun 7, 2011
- Lattice Semiconductor Corporation
- Howard Tang
- G11 - INFORMATION STORAGE
Information Patent Grant
Programmable logic device with a multi-data rate SDRAM interface
- Patent number 7,787,326
- Issue date Aug 31, 2010
- Lattice Semiconductor Corporation
- Brad Sharpe-Geisler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Programmable logic devices with custom identification systems and m...
- Patent number 7,702,977
- Issue date Apr 20, 2010
- Lattice Semiconductor Corporation
- Howard Tang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Programmable logic device with multiple slice types
- Patent number 7,696,784
- Issue date Apr 13, 2010
- Lattice Semiconductor Corporation
- Om P. Agrawal
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Dual-slice architectures for programmable logic devices
- Patent number 7,675,321
- Issue date Mar 9, 2010
- Lattice Semiconductor Corporation
- Om P. Agrawal
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Clock distribution chip for generating both zero-delay and non-zero...
- Patent number 7,657,773
- Issue date Feb 2, 2010
- Lattice Semiconductor Corporation
- Shyam Chandra
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Area efficient routing architectures for programmable logic devices
- Patent number 7,605,606
- Issue date Oct 20, 2009
- Lattice Semiconductor Corporation
- Ming H. Ding
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Logic block control architectures for programmable logic devices
- Patent number 7,592,834
- Issue date Sep 22, 2009
- Lattice Semiconductor Corporation
- Om P. Agrawal
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Programmable logic device with enhanced logic block architecture
- Patent number 7,573,291
- Issue date Aug 11, 2009
- Lattice Semiconductor Corporation
- Om Agrawal
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Programmable logic devices with user non-volatile memory
- Patent number 7,554,358
- Issue date Jun 30, 2009
- Lattice Semiconductor Corporation
- Fabiano Fontana
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Programmable logic devices with custom identification systems and m...
- Patent number 7,546,498
- Issue date Jun 9, 2009
- Lattice Semiconductor Corporation
- Howard Tang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Flexible memory architectures for programmable logic devices
- Patent number 7,495,970
- Issue date Feb 24, 2009
- Lattice Semiconductor Corporation
- Howard Tang
- G11 - INFORMATION STORAGE
Information Patent Grant
Programmable logic devices with transparent field reconfiguration
- Patent number 7,459,931
- Issue date Dec 2, 2008
- Lattice Semiconductor Corporation
- Howard Tang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Programmable logic devices with distributed memory
- Patent number 7,459,935
- Issue date Dec 2, 2008
- Lattice Semiconductor Corporation
- Om P. Agrawal
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Interface block architectures
- Patent number 7,427,874
- Issue date Sep 23, 2008
- Lattice Semiconductor Corporation
- Om P. Agrawal
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Logic block control architectures for programmable logic devices
- Patent number 7,397,276
- Issue date Jul 8, 2008
- Lattice Semiconductor Corporation
- Om P. Agrawal
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Dual slice architectures for programmable logic devices
- Patent number 7,385,417
- Issue date Jun 10, 2008
- Lattice Semiconductor Corporation
- Om P. Agrawal
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Programmable logic device architecture with multiple slice types
- Patent number 7,378,872
- Issue date May 27, 2008
- Lattice Semiconductor Corporation
- Om P. Agrawal
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Programmable logic device providing a serial peripheral interface
- Patent number 7,378,873
- Issue date May 27, 2008
- Lattice Semiconductor Corporation
- Howard Tang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Programmable logic devices with distributed memory and non-volatile...
- Patent number 7,355,441
- Issue date Apr 8, 2008
- Lattice Semiconductor Corporation
- Om P. Agrawal
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Programmable logic device with a double data rate SDRAM interface
- Patent number 7,342,838
- Issue date Mar 11, 2008
- Lattice Semiconductor Corporation
- Brad Sharpe-Geisler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Interface block architectures
- Patent number 7,327,159
- Issue date Feb 5, 2008
- Lattice Semiconductor Corporation
- Om P. Agrawal
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
SERDES with programmable I/O architecture
- Patent number 7,327,160
- Issue date Feb 5, 2008
- Lattice Semiconductor Corporation
- Om P. Agrawal
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Programmable logic device with enhanced logic block architecture
- Patent number 7,295,035
- Issue date Nov 13, 2007
- Lattice Semiconductor Corporation
- Om Agrawal
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Programmable interconnect architecture for programmable logic devices
- Patent number 7,256,613
- Issue date Aug 14, 2007
- Lattice Semiconductor Corporation
- Brad Sharpe-Geisler
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Upgradeable and reconfigurable programmable logic device
- Patent number 7,215,139
- Issue date May 8, 2007
- Lattice Semiconductor Corporation
- Om P. Agrawal
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
SERDES with programmable I/O architecture
- Patent number 7,208,975
- Issue date Apr 24, 2007
- Lattice Semiconductor Corporation
- Om P. Agrawal
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
FPGA integrated circuit having embedded sram memory blocks with reg...
- Patent number RE39510
- Issue date Mar 13, 2007
- Lattice Semiconductor Corporation
- Om P. Agrawal
- 326 - Electronic digital logic circuitry

Patents Applicationslast 30 patents

Information Patent Application
Upgradeable and reconfigurable programmable logic device
- Publication number 20060232295
- Publication date Oct 19, 2006
- Om P. Agrawal
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Upgradeable and reconfigurable programmable logic device
- Publication number 20050189962
- Publication date Sep 1, 2005
- Om P. Agrawal
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Clock generator with skew control
- Publication number 20050024105
- Publication date Feb 3, 2005
- Lattice Semiconductor Corporation
- Om P. Agrawal
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Clock generator
- Publication number 20050024118
- Publication date Feb 3, 2005
- Om P. Agrawal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Hierarchical general interconnect architecture for high density fpga's
- Publication number 20040010767
- Publication date Jan 15, 2004
- Lattice Semiconductor Corporation
- Om P. Agrawal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HIGH SPEED INTERFACE FOR A PROGRAMMABLE INTERCONNECT CIRCUIT
- Publication number 20030112031
- Publication date Jun 19, 2003
- Lattice Semiconductor Corporation
- Om P. Agrawal
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Enhanced macrocell module having expandable product term sharing ca...
- Publication number 20030107401
- Publication date Jun 12, 2003
- Lattice Semiconductor Corporation
- Om P. Agrawal
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Methods for configuring FPGA ' S having viriable grain components f...
- Publication number 20020196809
- Publication date Dec 26, 2002
- Vantis Corporation
- Om P. Agrawal
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Variable grain architecture for FPGA integrated circuits
- Publication number 20020186044
- Publication date Dec 12, 2002
- Vantis Corporation
- Om P. Agrawal
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Methods for configuring FPGA's having variable grain blocks and sha...
- Publication number 20010056570
- Publication date Dec 27, 2001
- Vantis Corporation
- Om P. Agrawal
- H03 - BASIC ELECTRONIC CIRCUITRY

Om P. Agrawal

Person

Patents Grantslast 30 patents

Clock distribution chip

Clock distribution chip

Flexible memory architectures for programmable logic devices

Programmable logic device with a multi-data rate SDRAM interface

Programmable logic devices with custom identification systems and m...

Programmable logic device with multiple slice types

Dual-slice architectures for programmable logic devices

Clock distribution chip for generating both zero-delay and non-zero...

Area efficient routing architectures for programmable logic devices

Logic block control architectures for programmable logic devices

Programmable logic device with enhanced logic block architecture

Programmable logic devices with user non-volatile memory

Programmable logic devices with custom identification systems and m...

Flexible memory architectures for programmable logic devices

Programmable logic devices with transparent field reconfiguration

Programmable logic devices with distributed memory

Interface block architectures

Logic block control architectures for programmable logic devices

Dual slice architectures for programmable logic devices

Programmable logic device architecture with multiple slice types

Programmable logic device providing a serial peripheral interface

Programmable logic devices with distributed memory and non-volatile...

Programmable logic device with a double data rate SDRAM interface

Interface block architectures

SERDES with programmable I/O architecture

Programmable logic device with enhanced logic block architecture

Programmable interconnect architecture for programmable logic devices

Upgradeable and reconfigurable programmable logic device

SERDES with programmable I/O architecture

FPGA integrated circuit having embedded sram memory blocks with reg...

Patents Applicationslast 30 patents

Upgradeable and reconfigurable programmable logic device

Upgradeable and reconfigurable programmable logic device

Clock generator with skew control

Clock generator

Hierarchical general interconnect architecture for high density fpga's

HIGH SPEED INTERFACE FOR A PROGRAMMABLE INTERCONNECT CIRCUIT

Enhanced macrocell module having expandable product term sharing ca...

Methods for configuring FPGA ' S having viriable grain components f...

Variable grain architecture for FPGA integrated circuits

Methods for configuring FPGA's having variable grain blocks and sha...