Oscar Frederick Jones JR.

Person

Colorado Springs, CO, US

People

Patents Grantslast 30 patents

Information Patent Grant
Dual-complementary integrating duty cycle detector with dead band n...
- Patent number 9,246,475
- Issue date Jan 26, 2016
- United Memories, Inc.
- Oscar Frederick Jones
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Data inversion register technique for integrated circuit memory tes...
- Patent number RE44726
- Issue date Jan 21, 2014
- Invensas Corporation
- Michael C. Parris
- 714 - Error detection/correction and fault detection/recovery
Information Patent Grant
Circuit and technique for reducing parity bit-widths for check bit...
- Patent number 8,510,641
- Issue date Aug 13, 2013
- Invensas Corporation
- Oscar Frederick Jones
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Clock controlled power-down state
- Patent number 6,788,122
- Issue date Sep 7, 2004
- United Memories, Inc.
- Oscar Frederick Jones
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Test interface for verification of high speed embedded synchronous...
- Patent number 6,732,305
- Issue date May 4, 2004
- United Memories, Inc.
- Oscar Frederick Jones
- G11 - INFORMATION STORAGE
Information Patent Grant
Time data compression technique for high speed integrated circuit m...
- Patent number 6,728,931
- Issue date Apr 27, 2004
- ProMos Technologies, Inc.
- Michael C. Parris
- G11 - INFORMATION STORAGE
Information Patent Grant
Refresh initiated precharge technique for dynamic random access mem...
- Patent number 6,667,927
- Issue date Dec 23, 2003
- United Memories, Inc.
- Oscar Frederick Jones
- G11 - INFORMATION STORAGE
Information Patent Grant
System and method for high speed integrated circuit device testing...
- Patent number 6,657,461
- Issue date Dec 2, 2003
- Mosel Vitelic Inc
- Oscar Frederick Jones
- G01 - MEASURING TESTING
Information Patent Grant
Simultaneous function dynamic random access memory device technique
- Patent number 6,643,212
- Issue date Nov 4, 2003
- United Memories, Inc.
- Oscar Frederick Jones
- G11 - INFORMATION STORAGE
Information Patent Grant
Look-ahead refresh for an integrated circuit memory
- Patent number 6,625,078
- Issue date Sep 23, 2003
- United Memories, Inc.
- Oscar Frederick Jones
- G11 - INFORMATION STORAGE
Information Patent Grant
Look-ahead, wrap-around first-in, first-out integrated (FIFO) circu...
- Patent number 6,622,198
- Issue date Sep 16, 2003
- United Memories, Inc.
- Oscar Frederick Jones
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Automatic delay technique for early read and write operations in sy...
- Patent number 6,608,797
- Issue date Aug 19, 2003
- United Memories, Inc.
- Michael C. Parris
- G11 - INFORMATION STORAGE
Information Patent Grant
Enhanced DRAM with embedded registers
- Patent number 6,347,357
- Issue date Feb 12, 2002
- Enhanced Memory Systems, Inc.
- Ronald H. Sartore
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Low skew signal generation circuit
- Patent number 6,339,346
- Issue date Jan 15, 2002
- United Memories, Inc.
- Oscar Frederick Jones
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Cached synchronous DRAM architecture having a mode register program...
- Patent number 6,289,413
- Issue date Sep 11, 2001
- International Business Machines Corp.
- Jim L. Rogers
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Enhanced DRAM with embedded registers
- Patent number 5,887,272
- Issue date Mar 23, 1999
- Enhanced Memory Systems, Inc.
- Ronald H. Sartore
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Enhanced DRAM with single row SRAM cache for all device read operat...
- Patent number 5,721,862
- Issue date Feb 24, 1998
- Ramtron International Corporation
- Ronald H. Sartore
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Enhanced DRAM with all reads from on-chip cache and all writers to...
- Patent number 5,699,317
- Issue date Dec 16, 1997
- Ramtron International Corporation
- Ronald H. Sartore
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and circuit for improved timing and noise margin in a DRAM
- Patent number 5,379,261
- Issue date Jan 3, 1995
- United Memories, Inc.
- Oscar F. Jones
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and circuit for configuring I/O devices
- Patent number 5,373,470
- Issue date Dec 13, 1994
- United Memories, Inc.
- Oscar F. Jones
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
DUAL-COMPLEMENTARY INTEGRATING DUTY CYCLE DETECTOR WITH DEAD BAND N...
- Publication number 20150295564
- Publication date Oct 15, 2015
- United Memories, Inc.
- Oscar Frederick Jones
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Static random access memory (SRAM) compatible, high availability me...
- Publication number 20060190678
- Publication date Aug 24, 2006
- Douglas Blaine Butler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Static random access memory (SRAM) compatible, high availability me...
- Publication number 20060190676
- Publication date Aug 24, 2006
- United Memories, Inc. Colorado Springs
- Douglas Blaine Butler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Cache and tag power-down function during low-power data retention s...
- Publication number 20060005053
- Publication date Jan 5, 2006
- Oscar Frederick Jones
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Low power sleep mode operation technique for dynamic random access...
- Publication number 20050286339
- Publication date Dec 29, 2005
- Michael C. Parris
- G11 - INFORMATION STORAGE
Information Patent Application
Dual access DRAM
- Publication number 20050286291
- Publication date Dec 29, 2005
- Michael C. Parris
- G11 - INFORMATION STORAGE
Information Patent Application
Non-contiguous masked refresh for an integrated circuit memory
- Publication number 20040184334
- Publication date Sep 23, 2004
- Michael C. Parris
- G11 - INFORMATION STORAGE
Information Patent Application
CLOCK CONTROLLED POWER-DOWN STATE
- Publication number 20040150448
- Publication date Aug 5, 2004
- Oscar Frederick Jones
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
SIMULTANEOUS FUNCTION DYNAMIC RANDOM ACCESS MEMORY DEVICE TECHNIQUE
- Publication number 20030198119
- Publication date Oct 23, 2003
- Oscar Frederick Jones
- G11 - INFORMATION STORAGE
Information Patent Application
LOOK-AHEAD REFRESH FOR AN INTEGRATED CIRCUIT MEMORY
- Publication number 20030161207
- Publication date Aug 28, 2003
- Oscar Frederick Jones
- G11 - INFORMATION STORAGE
Information Patent Application
Refresh initiated precharge technique for dynamic random access mem...
- Publication number 20030151965
- Publication date Aug 14, 2003
- Oscar Frederick Jones
- G11 - INFORMATION STORAGE
Information Patent Application
Time data compression technique for high speed integrated circuit m...
- Publication number 20020178413
- Publication date Nov 28, 2002
- Michael C. Parris
- G11 - INFORMATION STORAGE
Information Patent Application
System and method for high speed integrated circuit device testing...
- Publication number 20020135393
- Publication date Sep 26, 2002
- Oscar Frederick Jones
- G01 - MEASURING TESTING
Information Patent Application
Look-ahead, wrap-around first-in, first-out integrated (FIFO) circu...
- Publication number 20020138685
- Publication date Sep 26, 2002
- Oscar Frederick Jones
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Enhanced dram with embedded registers
- Publication number 20020056020
- Publication date May 9, 2002
- Ronald H. Sartore
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Test interface for verification of high speed embedded synchronous...
- Publication number 20020042898
- Publication date Apr 11, 2002
- Oscar Frederick Jones
- G11 - INFORMATION STORAGE

Oscar Frederick Jones JR.

Person

Patents Grantslast 30 patents

Dual-complementary integrating duty cycle detector with dead band n...

Data inversion register technique for integrated circuit memory tes...

Circuit and technique for reducing parity bit-widths for check bit...

Clock controlled power-down state

Test interface for verification of high speed embedded synchronous...

Time data compression technique for high speed integrated circuit m...

Refresh initiated precharge technique for dynamic random access mem...

System and method for high speed integrated circuit device testing...

Simultaneous function dynamic random access memory device technique

Look-ahead refresh for an integrated circuit memory

Look-ahead, wrap-around first-in, first-out integrated (FIFO) circu...

Automatic delay technique for early read and write operations in sy...

Enhanced DRAM with embedded registers

Low skew signal generation circuit

Cached synchronous DRAM architecture having a mode register program...

Enhanced DRAM with embedded registers

Enhanced DRAM with single row SRAM cache for all device read operat...

Enhanced DRAM with all reads from on-chip cache and all writers to...

Method and circuit for improved timing and noise margin in a DRAM

Method and circuit for configuring I/O devices

Patents Applicationslast 30 patents

DUAL-COMPLEMENTARY INTEGRATING DUTY CYCLE DETECTOR WITH DEAD BAND N...

Static random access memory (SRAM) compatible, high availability me...

Static random access memory (SRAM) compatible, high availability me...

Cache and tag power-down function during low-power data retention s...

Low power sleep mode operation technique for dynamic random access...

Dual access DRAM

Non-contiguous masked refresh for an integrated circuit memory

CLOCK CONTROLLED POWER-DOWN STATE

SIMULTANEOUS FUNCTION DYNAMIC RANDOM ACCESS MEMORY DEVICE TECHNIQUE

LOOK-AHEAD REFRESH FOR AN INTEGRATED CIRCUIT MEMORY

Refresh initiated precharge technique for dynamic random access mem...

Time data compression technique for high speed integrated circuit m...

System and method for high speed integrated circuit device testing...

Look-ahead, wrap-around first-in, first-out integrated (FIFO) circu...

Enhanced dram with embedded registers

Test interface for verification of high speed embedded synchronous...