Paolo Madoglio

Person

Beaverton, OR, US

People

Patents Grantslast 30 patents

Information Patent Grant
Modulation circuitry with N.5 division
- Patent number 10,886,878
- Issue date Jan 5, 2021
- Intel IP Corporation
- Georgios Yorgos Palaskas
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Direct digital frequency generation using time and amplitude
- Patent number 10,230,520
- Issue date Mar 12, 2019
- Intel IP Corporation
- Hasnain Lakdawala
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Digital time converter systems and methods
- Patent number 10,177,774
- Issue date Jan 8, 2019
- Intel IP Corporation
- Georgios Yorgos Palaskas
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Power saving technique for digital to time converters
- Patent number 9,847,676
- Issue date Dec 19, 2017
- Intel IP Corporation
- Paolo Madoglio
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
Information Patent Grant
Direct digital frequency generation using time and amplitude
- Patent number 9,660,798
- Issue date May 23, 2017
- Intel IP Corporation
- Hasnain Lakdawala
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Digital time converter systems and method
- Patent number 9,641,185
- Issue date May 2, 2017
- Intel IP Corporation
- Georgios Yorgos Palaskas
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Phase multiplexer
- Patent number 9,438,265
- Issue date Sep 6, 2016
- Intel Corporation
- Paolo Madoglio
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Direct digital frequency generation using time and amplitude
- Patent number 9,288,841
- Issue date Mar 15, 2016
- Intel IP Corporation
- Hasnain Lakdawala
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Segmented digital-to-time converter calibration
- Patent number 9,209,958
- Issue date Dec 8, 2015
- Intel Corporation
- Georgios Palaskas
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Redundant delay digital-to-time converter
- Patent number 9,130,588
- Issue date Sep 8, 2015
- Intel Mobile Communications GmbH
- Stephan Henzler
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Parallel digital-to-time converter architecture
- Patent number 9,054,925
- Issue date Jun 9, 2015
- Intel Corporation
- Paolo Madoglio
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Digital delay-locked loop with drift sensor
- Patent number 8,598,930
- Issue date Dec 3, 2013
- Intel Corporation
- Stefano Pellerano
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Sub-picosecond resolution segmented re-circulating stochastic time-...
- Patent number 8,390,349
- Issue date Mar 5, 2013
- Intel Corporation
- Ashoke Ravi
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
System, method and apparatus for an open loop calibrated phase wrap...
- Patent number 8,222,966
- Issue date Jul 17, 2012
- Intel Corporation
- Ashoke Ravi
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Digital phase lock loop
- Patent number 8,207,770
- Issue date Jun 26, 2012
- Intel Corporation
- Ashoke Ravi
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Dynamic element matching for time-to-digital converters
- Patent number 8,198,929
- Issue date Jun 12, 2012
- Intel Corporation
- Stefano Pellerano
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
METHOD AND APPARATUS FOR SKEW ERROR MEASUREMENT IN A DIGITAL-TO-ANA...
- Publication number 20250183904
- Publication date Jun 5, 2025
- Intel Corporation
- Daniel GRUBER
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
DIGITAL PHASED ARRAY
- Publication number 20230283311
- Publication date Sep 7, 2023
- Benjamin Jann
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
PAPR REDUCTION FOR CORRELATED CDM GROUPS
- Publication number 20230208693
- Publication date Jun 29, 2023
- Peter Pawliuk
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
CONFIGURABLE HYBRID BEAMFORMING
- Publication number 20230199516
- Publication date Jun 22, 2023
- Intel Corporation
- Gregory Chance
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
MODULATION CIRCUITRY WITH N.5 DIVISION
- Publication number 20190214944
- Publication date Jul 11, 2019
- Intel IP Corporation
- Georgios Yorgos Palaskas
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
DIGITAL TIME CONVERTER SYSTEMS AND METHODS
- Publication number 20180006658
- Publication date Jan 4, 2018
- Intel IP Corporation
- Georgios Yorgos Palaskas
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
DIRECT DIGITAL FREQUENCY GENERATION USING TIME AND AMPLITUDE
- Publication number 20170237549
- Publication date Aug 17, 2017
- Intel IP Corporation
- Hasnain Lakdawala
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
DIRECT DIGITAL FREQUENCY GENERATION USING TIME AND AMPLITUDE
- Publication number 20160261401
- Publication date Sep 8, 2016
- Intel IP Corporation
- Hasnain Lakdawala
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
SEGMENTED DIGITAL-TO-TIME CONVERTER CALIBRATION
- Publication number 20150381337
- Publication date Dec 31, 2015
- Intel Corporation
- Paolo Madoglio
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
PHASE MULTIPLEXER
- Publication number 20150303939
- Publication date Oct 22, 2015
- Intel Corporation
- Paolo MADOGLIO
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DIRECT DIGITAL FREQUENCY GENERATION USING TIME AND AMPLITUDE
- Publication number 20150181643
- Publication date Jun 25, 2015
- Hasnain Lakdawala
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
PARALLEL DIGITAL-TO-TIME CONVERTER ARCHITECTURE
- Publication number 20150156044
- Publication date Jun 4, 2015
- Paolo Madoglio
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
POWER SAVING TECHNIQUE FOR DIGITAL TO TIME CONVERTERS
- Publication number 20150091384
- Publication date Apr 2, 2015
- Paolo Madoglio
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
Information Patent Application
DIGITAL DELAY-LOCKED LOOP WITH DRIFT SENSOR
- Publication number 20130271194
- Publication date Oct 17, 2013
- Stefano Pellerano
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
DIGITAL PHASE LOCK LOOP
- Publication number 20120161831
- Publication date Jun 28, 2012
- Ashoke Ravi
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
SYSTEM, METHOD AND APPARATUS FOR AN OPEN LOOP CALIBRATED PHASE WRAP...
- Publication number 20120062331
- Publication date Mar 15, 2012
- Ashoke Ravi
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
DYNAMIC ELEMENT MATCHING FOR TIME-TO-DIGITAL CONVERTERS
- Publication number 20120049914
- Publication date Mar 1, 2012
- Stefano Pellerano
- H03 - BASIC ELECTRONIC CIRCUITRY

Paolo Madoglio

Person

Patents Grantslast 30 patents

Modulation circuitry with N.5 division

Direct digital frequency generation using time and amplitude

Digital time converter systems and methods

Power saving technique for digital to time converters

Direct digital frequency generation using time and amplitude

Digital time converter systems and method

Phase multiplexer

Direct digital frequency generation using time and amplitude

Segmented digital-to-time converter calibration

Redundant delay digital-to-time converter

Parallel digital-to-time converter architecture

Digital delay-locked loop with drift sensor

Sub-picosecond resolution segmented re-circulating stochastic time-...

System, method and apparatus for an open loop calibrated phase wrap...

Digital phase lock loop

Dynamic element matching for time-to-digital converters

Patents Applicationslast 30 patents

METHOD AND APPARATUS FOR SKEW ERROR MEASUREMENT IN A DIGITAL-TO-ANA...

DIGITAL PHASED ARRAY

PAPR REDUCTION FOR CORRELATED CDM GROUPS

CONFIGURABLE HYBRID BEAMFORMING

MODULATION CIRCUITRY WITH N.5 DIVISION

DIGITAL TIME CONVERTER SYSTEMS AND METHODS

DIRECT DIGITAL FREQUENCY GENERATION USING TIME AND AMPLITUDE

DIRECT DIGITAL FREQUENCY GENERATION USING TIME AND AMPLITUDE

SEGMENTED DIGITAL-TO-TIME CONVERTER CALIBRATION

PHASE MULTIPLEXER

DIRECT DIGITAL FREQUENCY GENERATION USING TIME AND AMPLITUDE

PARALLEL DIGITAL-TO-TIME CONVERTER ARCHITECTURE

POWER SAVING TECHNIQUE FOR DIGITAL TO TIME CONVERTERS

DIGITAL DELAY-LOCKED LOOP WITH DRIFT SENSOR

DIGITAL PHASE LOCK LOOP

SYSTEM, METHOD AND APPARATUS FOR AN OPEN LOOP CALIBRATED PHASE WRAP...

DYNAMIC ELEMENT MATCHING FOR TIME-TO-DIGITAL CONVERTERS