Patrick R. Marchand

Person

Apex, NC, US

People

Patents Grantslast 30 patents

Information Patent Grant
Compression status bit cache and backing store
- Patent number 10,515,011
- Issue date Dec 24, 2019
- NVIDIA Corporation
- David B. Glasco
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus for adapting pipeline stage latency based on...
- Patent number 9,329,866
- Issue date May 3, 2016
- Altera Corporation
- Edwin Franklin Barry
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus for scalable array processor interrupt detect...
- Patent number 9,158,547
- Issue date Oct 13, 2015
- Altera Corporation
- Edwin Franklin Barry
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
System core for transferring data between an external device and me...
- Patent number 9,009,365
- Issue date Apr 14, 2015
- Altera Corporation
- Gerald George Pechanek
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Isochronous hub contracts
- Patent number 8,963,940
- Issue date Feb 24, 2015
- NVIDIA Corporation
- Duncan A. Riach
- G09 - EDUCATION CRYPTOGRAPHY DISPLAY ADVERTISING SEALS
Information Patent Grant
Techniques for evicting dirty data from a cache using a notificatio...
- Patent number 8,949,541
- Issue date Feb 3, 2015
- NVIDIA Corporation
- David B. Glasco
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Padding buffer requests to avoid reads of invalid data
- Patent number 8,874,844
- Issue date Oct 28, 2014
- NVIDIA Corporation
- David B. Glasco
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-class data cache policies
- Patent number 8,868,838
- Issue date Oct 21, 2014
- NVIDIA Corporation
- David B. Glasco
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Compression status caching
- Patent number 8,862,823
- Issue date Oct 14, 2014
- NVIDIA Corporation
- David B. Glasco
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus for scalable array processor interrupt detect...
- Patent number 8,751,772
- Issue date Jun 10, 2014
- Altera Corporation
- Edwin Franklin Barry
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Compression status bit cache and backing store
- Patent number 8,700,862
- Issue date Apr 15, 2014
- NVIDIA Corporation
- David B. Glasco
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Efficient line and page organization for compression status bit cac...
- Patent number 8,627,041
- Issue date Jan 7, 2014
- NVIDIA Corporation
- David B. Glasco
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Compression status bit cache with deterministic isochronous latency
- Patent number 8,595,437
- Issue date Nov 26, 2013
- NVIDIA Corporation
- David B. Glasco
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Virtual channels for effective packet transfer
- Patent number 8,539,130
- Issue date Sep 17, 2013
- NVIDIA Corporation
- David B. Glasco
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Storing dynamically sized buffers within a cache
- Patent number 8,504,773
- Issue date Aug 6, 2013
- NVIDIA Corporation
- David B. Glasco
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus for scalable array processor interrupt detect...
- Patent number 8,489,858
- Issue date Jul 16, 2013
- Altera Corporation
- Edwin Franklin Barry
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Cache and associated method with frame buffer managed dirty data pu...
- Patent number 8,464,001
- Issue date Jun 11, 2013
- Nvidia Corporation
- John H. Edmondson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus for adapting pipeline stage latency based on...
- Patent number 8,413,086
- Issue date Apr 2, 2013
- Altera Corporation
- Edwin Franklin Barry
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System core for transferring data between an external device and me...
- Patent number 8,397,000
- Issue date Mar 12, 2013
- Altera Corporation
- Gerald George Pechanek
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Deadlock avoidance by marking CPU traffic as special
- Patent number 8,392,667
- Issue date Mar 5, 2013
- NVIDIA Corporation
- Samuel H. Duncan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System core for transferring data between an external device and me...
- Patent number 8,296,479
- Issue date Oct 23, 2012
- Altera Corporation
- Gerald George Pechanek
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for converting data formats using a shared cache...
- Patent number 8,271,734
- Issue date Sep 18, 2012
- NVIDIA Corporation
- David B. Glasco
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for cleaning dirty data in an intermediate cache...
- Patent number 8,244,984
- Issue date Aug 14, 2012
- NVIDIA Corporation
- David B. Glasco
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Using a data cache array as a DRAM load/store buffer
- Patent number 8,234,478
- Issue date Jul 31, 2012
- NVIDIA Corporation
- James Roberts
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus for scalable array processor interrupt detect...
- Patent number 8,161,267
- Issue date Apr 17, 2012
- Altera Corporation
- Edwin Franklin Barry
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
L2 ECC implementation
- Patent number 8,156,404
- Issue date Apr 10, 2012
- NVIDIA Corporation
- David B. Glasco
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cache-based control of atomic operations in conjunction with an ext...
- Patent number 8,135,926
- Issue date Mar 13, 2012
- NVIDIA Corporation
- David B. Glasco
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Configurable cache occupancy policy
- Patent number 8,131,931
- Issue date Mar 6, 2012
- NVIDIA Corporation
- James Roberts
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System core for transferring data between an external device and me...
- Patent number 8,117,357
- Issue date Feb 14, 2012
- Altera Corporation
- Gerald George Pechanek
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cache-based control of atomic operations in conjunction with an ext...
- Patent number 8,108,610
- Issue date Jan 31, 2012
- NVIDIA Corporation
- David B. Glasco
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
COMPRESSION STATUS BIT CACHE AND BACKING STORE
- Publication number 20140237189
- Publication date Aug 21, 2014
- NVIDIA Corporation
- David B. GLASCO
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Methods and Apparatus for Scalable Array Processor Interrupt Detect...
- Publication number 20140237215
- Publication date Aug 21, 2014
- Altera Corporation
- Edwin Franklin Barry
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Methods and Apparatus for Adapting Pipeline Stage Latency Based on...
- Publication number 20140075157
- Publication date Mar 13, 2014
- Altera Corporation
- Edwin Franklin Barry
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
System Core for Transferring Data Between an External Device and Me...
- Publication number 20140059324
- Publication date Feb 27, 2014
- Gerald George Pechanek
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Methods and Apparatus for Scalable Array Processor Interrupt Detect...
- Publication number 20130283012
- Publication date Oct 24, 2013
- Altera Corporation
- Edwin Franklin Barry
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Class Dependent Clean and Dirty Policy
- Publication number 20130124802
- Publication date May 16, 2013
- David B. Glasco
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
System Core for Transferring Data Between an External Device and Me...
- Publication number 20130007331
- Publication date Jan 3, 2013
- Altera Corporation
- Gerald G. Pechanek
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Methods and Apparatus for Scalable Array Processor Interrupt Detect...
- Publication number 20120173849
- Publication date Jul 5, 2012
- Altera Corporation
- Edwin Frank Barry
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
System Core for Transferring Data Between an External Device and Me...
- Publication number 20120124335
- Publication date May 17, 2012
- Altera Corporation
- Gerald G. Pechanek
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
System Core for Transferring Data Between an External Device and Me...
- Publication number 20110219210
- Publication date Sep 8, 2011
- Altera Corporation
- Gerald G. Pechanek
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
EFFICIENT LINE AND PAGE ORGANIZATION FOR COMPRESSION STATUS BIT CAC...
- Publication number 20110087840
- Publication date Apr 14, 2011
- David B. GLASCO
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
VIRTUAL CHANNELS FOR EFFECTIVE PACKET TRANSFER
- Publication number 20110072177
- Publication date Mar 24, 2011
- David B. Glasco
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Methods and Apparatus for Scalable Array Processor Interrupt Detect...
- Publication number 20110072250
- Publication date Mar 24, 2011
- Altera Corporation
- Edwin Frank Barry
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Methods and Apparatus for Adapting Pipeline Stage Latency Based on...
- Publication number 20100318775
- Publication date Dec 16, 2010
- Altera Corporation
- Edwin Franklin Barry
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Deadlock Avoidance By Marking CPU Traffic As Special
- Publication number 20100153658
- Publication date Jun 17, 2010
- Samuel H. Duncan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Compression Status Bit Cache And Backing Store
- Publication number 20100138614
- Publication date Jun 3, 2010
- David B. Glasco
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
System core for transferring data between an external device and me...
- Publication number 20090063724
- Publication date Mar 5, 2009
- Gerald G. Pechanek
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Methods and Apparatus for Scalable Array Processor Interrupt Detect...
- Publication number 20080222333
- Publication date Sep 11, 2008
- Altera Corporation
- Edwin Frank Barry
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Methods and Apparatus for a Bit Rake Instruction
- Publication number 20080120494
- Publication date May 22, 2008
- Altera Corporation
- Patrick R. Marchand
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Methods and apparatus for power control in a scalable array of proc...
- Publication number 20050223253
- Publication date Oct 6, 2005
- PTS Corporation
- Patrick R. Marchand
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Specifying different type generalized event and action pair in a pr...
- Publication number 20050125644
- Publication date Jun 9, 2005
- PTS Corporation
- Edwin F. Barry
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Methods and apparatus for scalable array processor interrupt detect...
- Publication number 20050027973
- Publication date Feb 3, 2005
- PTS Corporation
- Edwin Frank Barry
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Methods and apparatus for establishing port priority functions in a...
- Publication number 20040093484
- Publication date May 13, 2004
- PTS Corporation
- Edwin Frank Barry
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Methods and apparatus to dynamically reconfigure the instruction pi...
- Publication number 20030061473
- Publication date Mar 27, 2003
- Juan Guillermo Revilla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Methods and apparatus for power control in a scalable array of proc...
- Publication number 20020004916
- Publication date Jan 10, 2002
- Patrick R. Marchand
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Methods and apparatus for scalable array processor interrupt detect...
- Publication number 20010049763
- Publication date Dec 6, 2001
- Edwin Frank Barry
- G06 - COMPUTING CALCULATING COUNTING

Patrick R. Marchand

Person

Patents Grantslast 30 patents

Compression status bit cache and backing store

Methods and apparatus for adapting pipeline stage latency based on...

Methods and apparatus for scalable array processor interrupt detect...

System core for transferring data between an external device and me...

Isochronous hub contracts

Techniques for evicting dirty data from a cache using a notificatio...

Padding buffer requests to avoid reads of invalid data

Multi-class data cache policies

Compression status caching

Methods and apparatus for scalable array processor interrupt detect...

Compression status bit cache and backing store

Efficient line and page organization for compression status bit cac...

Compression status bit cache with deterministic isochronous latency

Virtual channels for effective packet transfer

Storing dynamically sized buffers within a cache

Methods and apparatus for scalable array processor interrupt detect...

Cache and associated method with frame buffer managed dirty data pu...

Methods and apparatus for adapting pipeline stage latency based on...

System core for transferring data between an external device and me...

Deadlock avoidance by marking CPU traffic as special

System core for transferring data between an external device and me...

Method and system for converting data formats using a shared cache...

System and method for cleaning dirty data in an intermediate cache...

Using a data cache array as a DRAM load/store buffer

Methods and apparatus for scalable array processor interrupt detect...

L2 ECC implementation

Cache-based control of atomic operations in conjunction with an ext...

Configurable cache occupancy policy

System core for transferring data between an external device and me...

Cache-based control of atomic operations in conjunction with an ext...

Patents Applicationslast 30 patents

COMPRESSION STATUS BIT CACHE AND BACKING STORE

Methods and Apparatus for Scalable Array Processor Interrupt Detect...

Methods and Apparatus for Adapting Pipeline Stage Latency Based on...

System Core for Transferring Data Between an External Device and Me...

Methods and Apparatus for Scalable Array Processor Interrupt Detect...

Class Dependent Clean and Dirty Policy

System Core for Transferring Data Between an External Device and Me...

Methods and Apparatus for Scalable Array Processor Interrupt Detect...

System Core for Transferring Data Between an External Device and Me...

System Core for Transferring Data Between an External Device and Me...

EFFICIENT LINE AND PAGE ORGANIZATION FOR COMPRESSION STATUS BIT CAC...

VIRTUAL CHANNELS FOR EFFECTIVE PACKET TRANSFER

Methods and Apparatus for Scalable Array Processor Interrupt Detect...

Methods and Apparatus for Adapting Pipeline Stage Latency Based on...

Deadlock Avoidance By Marking CPU Traffic As Special

Compression Status Bit Cache And Backing Store

System core for transferring data between an external device and me...

Methods and Apparatus for Scalable Array Processor Interrupt Detect...

Methods and Apparatus for a Bit Rake Instruction

Methods and apparatus for power control in a scalable array of proc...

Specifying different type generalized event and action pair in a pr...

Methods and apparatus for scalable array processor interrupt detect...

Methods and apparatus for establishing port priority functions in a...

Methods and apparatus to dynamically reconfigure the instruction pi...

Methods and apparatus for power control in a scalable array of proc...

Methods and apparatus for scalable array processor interrupt detect...