Patrick Variot

Person

San Jose, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
3D-interconnect with electromagnetic interference (“EMI”) shield an...
- Patent number 12,040,284
- Issue date Jul 16, 2024
- Invensas LLC
- Patrick Variot
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Region shielding within a package of a microelectronic device
- Patent number 12,021,041
- Issue date Jun 25, 2024
- Invensas LLC
- Patrick Variot
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
3D-interconnect
- Patent number 11,929,337
- Issue date Mar 12, 2024
- Invensas LLC
- Chok J. Chia
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
3D-interconnect
- Patent number 11,031,362
- Issue date Jun 8, 2021
- Invensas Corporation
- Chok J. Chia
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
3D-interconnect
- Patent number 10,181,447
- Issue date Jan 15, 2019
- Invensas Corporation
- Chok J. Chia
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Electronic device package and method of manufacture
- Patent number 8,384,205
- Issue date Feb 26, 2013
- LSI Corporation
- Qwai Low
- Y10 - TECHNICAL SUBJECTS COVERED BY FORMER USPC
Information Patent Grant
Electronic device package and method of manufacture
- Patent number 7,993,981
- Issue date Aug 9, 2011
- LSI Corporation
- Qwai Low
- Y10 - TECHNICAL SUBJECTS COVERED BY FORMER USPC
Information Patent Grant
Method for programming a substrate for array-type packages
- Patent number 6,492,253
- Issue date Dec 10, 2002
- LSI Logic Corporation
- Chok J. Chia
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Molded tape ball grid array package
- Patent number 6,489,571
- Issue date Dec 3, 2002
- LSI Logic Corporation
- Chok J. Chia
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Bondable anodized aluminum heatspreader for semiconductor packages
- Patent number 6,297,550
- Issue date Oct 2, 2001
- LSI Logic Corporation
- Chok J. Chia
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Electrostatic protected substrate
- Patent number 6,143,586
- Issue date Nov 7, 2000
- LSI Logic Corporation
- Chok J. Chia
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Apparatus and method for testing a flip chip integrated circuit pac...
- Patent number 6,117,695
- Issue date Sep 12, 2000
- LSI Logic Corporation
- Adrian S. Murphy
- G01 - MEASURING TESTING
Information Patent Grant
Electroplating fixture for high density substrates
- Patent number 6,110,815
- Issue date Aug 29, 2000
- LSI Logic Corporation
- Chok J. Chia
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for planarizing an array of solder balls
- Patent number 6,088,914
- Issue date Jul 18, 2000
- LSI Logic Corporation
- Patrick Variot
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Programmable substrate for array-type packages
- Patent number 6,054,767
- Issue date Apr 25, 2000
- LSI Logic Corp.
- Chok J. Chia
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for compensating for bottom warpage of a BGA integrated circuit
- Patent number 5,989,937
- Issue date Nov 23, 1999
- LSI Logic Corporation
- Patrick Variot
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Process for using a removeable plating bus layer for high density s...
- Patent number 5,981,311
- Issue date Nov 9, 1999
- LSI Logic Corporation
- Chok J. Chia
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of providing electrical connection between an integrated cir...
- Patent number 5,933,710
- Issue date Aug 3, 1999
- LSI Logic Corporation
- Chok J. Chia
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for planarizing an array of solder balls
- Patent number 5,901,437
- Issue date May 11, 1999
- LSI Logic Corporation
- Patrick Variot
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Thin power tape ball grid array package
- Patent number 5,869,889
- Issue date Feb 9, 1999
- LSI Logic Corporation
- Chok J. Chia
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Ball grid array package employing solid core solder balls
- Patent number 5,841,198
- Issue date Nov 24, 1998
- LSI Logic Corporation
- Chok J. Chia
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Surface mount peripheral leaded and ball grid array package
- Patent number 5,789,811
- Issue date Aug 4, 1998
- LSI Logic Corporation
- Chok J. Chia
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of planarizing an array of plastically deformable contacts o...
- Patent number 5,745,986
- Issue date May 5, 1998
- LSI Logic Corporation
- Patrick Variot
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for encapsulating an integrated circuit package
- Patent number 5,692,296
- Issue date Dec 2, 1997
- LSI Logic Corporation
- Patrick Variot
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Apparatus for encapsulating an integrated circuit package
- Patent number 5,570,272
- Issue date Oct 29, 1996
- LSI Logic Corporation
- Patrick Variot
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Surface mount peripheral leaded and ball grid array package
- Patent number 5,563,446
- Issue date Oct 8, 1996
- LSI Logic Corporation
- Chok J. Chia
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Overmolded semiconductor package
- Patent number 5,557,150
- Issue date Sep 17, 1996
- LSI Logic Corporation
- Patrick Variot
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
Method for encapsulating an integrated circuit package
- Patent number 5,527,743
- Issue date Jun 18, 1996
- LSI Logic Corporation
- Patrick Variot
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit having a coplanar solder ball contact array
- Patent number 5,435,482
- Issue date Jul 25, 1995
- LSI Logic Corporation
- Patrick Variot
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
GPT system for encapsulating an integrated circuit package
- Patent number 5,420,752
- Issue date May 30, 1995
- LSI Logic Corporation
- Patrick Variot
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
3D-INTERCONNECT
- Publication number 20250015031
- Publication date Jan 9, 2025
- ADEIA SEMICONDUCTOR TECHNOLOGIES LLC
- Chok J. Chia
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
3D-INTERCONNECT WITH ELECTROMAGNETIC INTERFERENCE ("EMI") SHIELD AN...
- Publication number 20240339418
- Publication date Oct 10, 2024
- Invensas LLC
- Patrick Variot
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
REGION SHIELDING WITHIN A PACKAGE OF A MICROELECTRONIC DEVICE
- Publication number 20240312928
- Publication date Sep 19, 2024
- Invensas LLC
- Patrick Variot
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HEAT DISSIPATING SYSTEM FOR ELECTRONIC DEVICES
- Publication number 20230245950
- Publication date Aug 3, 2023
- ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.
- Belgacem HABA
- F28 - HEAT EXCHANGE IN GENERAL
Information Patent Application
THERMOELECTRIC COOLING FOR DIE PACKAGES
- Publication number 20230197559
- Publication date Jun 22, 2023
- ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.
- Belgacem Haba
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
3D-Interconnect with Electromagnetic Interference ("EMI") Shield an...
- Publication number 20230154862
- Publication date May 18, 2023
- Invensas Corporation
- Patrick Variot
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
RADIO FREQUENCY DEVICE PACKAGES
- Publication number 20230130259
- Publication date Apr 27, 2023
- Invensas LLC
- Belgacem Haba
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
REGION SHIELDING WITHIN A PACKAGE OF A MICROELECTRONIC DEVICE
- Publication number 20220139846
- Publication date May 5, 2022
- Invensas Corporation
- Patrick Variot
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
3d-Interconnect
- Publication number 20210366857
- Publication date Nov 25, 2021
- Invensas Corporation
- Chok J. Chia
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
3D-Interconnect
- Publication number 20190148324
- Publication date May 16, 2019
- Invensas Corporation
- Chok J. Chia
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
3D-INTERCONNECT
- Publication number 20180308813
- Publication date Oct 25, 2018
- Invensas Corporation
- Chok J. Chia
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FLIP-CHIP PACKAGE AND METHOD OF MANUFACTURING THE SAME USING ABLATION
- Publication number 20120018901
- Publication date Jan 26, 2012
- LSI Corporation
- Patrick Variot
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ELECTRONIC DEVICE PACKAGE AND METHOD OF MANUFACTURE
- Publication number 20110260324
- Publication date Oct 27, 2011
- LSI Corporation
- Qwai Low
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ELECTRONIC DEVICE PACKAGE AND METHOD OF MANUFACTURE
- Publication number 20100314747
- Publication date Dec 16, 2010
- LSI Corporation
- Qwai Low
- H01 - BASIC ELECTRIC ELEMENTS

Patrick Variot

Person

Patents Grantslast 30 patents

3D-interconnect with electromagnetic interference (“EMI”) shield an...

Region shielding within a package of a microelectronic device

3D-interconnect

3D-interconnect

3D-interconnect

Electronic device package and method of manufacture

Electronic device package and method of manufacture

Method for programming a substrate for array-type packages

Molded tape ball grid array package

Bondable anodized aluminum heatspreader for semiconductor packages

Electrostatic protected substrate

Apparatus and method for testing a flip chip integrated circuit pac...

Electroplating fixture for high density substrates

Method for planarizing an array of solder balls

Programmable substrate for array-type packages

Method for compensating for bottom warpage of a BGA integrated circuit

Process for using a removeable plating bus layer for high density s...

Method of providing electrical connection between an integrated cir...

Method for planarizing an array of solder balls

Thin power tape ball grid array package

Ball grid array package employing solid core solder balls

Surface mount peripheral leaded and ball grid array package

Method of planarizing an array of plastically deformable contacts o...

Method for encapsulating an integrated circuit package

Apparatus for encapsulating an integrated circuit package

Surface mount peripheral leaded and ball grid array package

Overmolded semiconductor package

Method for encapsulating an integrated circuit package

Integrated circuit having a coplanar solder ball contact array

GPT system for encapsulating an integrated circuit package

Patents Applicationslast 30 patents

3D-INTERCONNECT

3D-INTERCONNECT WITH ELECTROMAGNETIC INTERFERENCE ("EMI") SHIELD AN...

REGION SHIELDING WITHIN A PACKAGE OF A MICROELECTRONIC DEVICE

HEAT DISSIPATING SYSTEM FOR ELECTRONIC DEVICES

THERMOELECTRIC COOLING FOR DIE PACKAGES

3D-Interconnect with Electromagnetic Interference ("EMI") Shield an...

RADIO FREQUENCY DEVICE PACKAGES

REGION SHIELDING WITHIN A PACKAGE OF A MICROELECTRONIC DEVICE

3d-Interconnect

3D-Interconnect

3D-INTERCONNECT

FLIP-CHIP PACKAGE AND METHOD OF MANUFACTURING THE SAME USING ABLATION

ELECTRONIC DEVICE PACKAGE AND METHOD OF MANUFACTURE

ELECTRONIC DEVICE PACKAGE AND METHOD OF MANUFACTURE