Patent Grant
11929337
The subject matter of the present application relates to microelectronic assemblies and fabrication methods, and more particularly to the structure of and fabrication method for a low-profile microelectronic package.
Semiconductor chips are commonly provided as individual, prepackaged units. A standard chip has a flat, rectangular body with a large front face having contacts connected to the internal circuitry of the chip. Each individual chip typically is mounted in a package which, in turn, is mounted on a circuit panel such as a printed circuit board and which connects the contacts of the chip to conductors of the circuit panel.
Each chip package has many electrical connections for carrying signals, power and ground between terminals and the chips therein. The electrical connections can include different kinds of conductors such as horizontal conductors, e.g., traces, beam leads, etc., which extend in a horizontal direction relative to a contact-bearing surface of a chip, vertical conductors such as vias, which extend in a vertical direction relative to the surface of the chip, and wire bonds which extend in both horizontal and vertical directions relative to the surface of the chip.
In many conventional designs, the chip package occupies an area of the circuit panel considerably larger than the area of the chip itself. In some designs which are referred to as “flip chip” designs, the front face of the chip confronts the face of a package substrate, and the contacts on the chip are bonded directly to contacts of the package substrate by solder balls or other connecting elements. In turn, the package substrate can be bonded to a circuit panel through terminals overlying the front face of the chip.
There are, however, applications in which a relatively larger package is desired. These include instances in which a relatively large fan-out area is needed to achieve connection to a larger array on a printed circuit board or the like. Many wafer-level packages present reliability issues in such relatively larger sizes due to an inherent increase in the effects of varying coefficients of thermal expansion among the components of the package. Such effects can also be visible in relatively smaller applications, particularly when contacts are placed in certain locations and when the package undergoes frequent heat-cycling.
Size is a significant consideration in any physical arrangement of one or more chips. The demand for more compact physical arrangements of chips has become even more intense with the rapid progress of portable electronic devices. Merely by way of example, devices commonly referred to as “smart phones” integrate the functions of a cellular telephone with powerful data processors, memory and ancillary devices such as global positioning system receivers, electronic cameras, and local area network connections along with high-resolution displays and associated image processing chips. Such devices can provide capabilities such as full internet connectivity, entertainment including full-resolution video, navigation, electronic banking and more, all in a pocket-size device. Complex portable devices require packing numerous chips into a small space. Moreover, some of the chips have many input and output connections, commonly referred to as “I/Os.” These I/Os must be interconnected with the I/Os of other chips. The components which form the interconnections should not greatly increase the size of the assembly. Similar needs arise in other applications as, for example, in data servers such as those used in internet search engines where increased performance and size reduction are needed.
In light of the foregoing, certain improvements can be made in the structure of microelectronic packages and assemblies which comprise a microelectronic package. In this regard, there remains a need for improved packages that are reliable, thin, testable and economical to manufacture.
According to an aspect of the disclosure, a method of making a microelectronic package includes positioning a microelectronic element on a carrier; providing a conductive structure that overlies at least a portion of the microelectronic element and the carrier, the conductive structure having a base and a plurality of interconnection elements, the plurality of interconnection elements extending away from the base toward free ends that are positioned adjacent the carrier, the plurality of interconnection elements spaced apart from one another by a plurality of recesses; filling the plurality of recesses with an encapsulant such that the base overlies a first surface of the encapsulant and the plurality of interconnection elements are encapsulated within the encapsulant; removing the carrier to expose bond pads of the microelectronic element overlying the carrier, the free ends of the interconnection elements, and a second surface of the encapsulant opposed to the first surface; providing a redistribution structure to conductively connect exposed ends of the interconnection elements with terminals of the microelectronic package; and patterning the base of the conductive structure overlying the first surface of the encapsulant to provide external contacts of the microelectronic package.
In accordance with one or more particular aspects, the interconnection elements may have a first height greater than a second height of the microelectronic element.
In accordance with one or more particular aspects, positioning the microelectronic element further comprises positioning an active surface of the microelectronic element towards the carrier, such that bond pads of the microelectronic element are adjacent the carrier. At least some of the external contacts may overlie a rear surface of the microelectronic element. The patterning can include patterning a conductive routing layer overlying the microelectronic element. The conductive structure may overlie a rear surface of the microelectronic element such that there is a space between the rear surface of the microelectronic element and a surface of the base of the conductive structure, and wherein filling the plurality of recesses includes filing the space with encapsulant. A thermal interface material may be provided over a rear surface opposite the active surface of the microelectronic element such that the conductive structure overlies the thermal interface material. Filling the plurality of recesses may include filing a recess of the plurality of recesses in which the microelectronic element is encapsulated such that the encapsulant is adjacent edges of the microelectronic element and edges of the thermal interface material.
In accordance with one or more particular aspects of the disclosure, the method may further include positioning the microelectronic element within one of the plurality of recesses of the conductive structure, each of the recesses bounded by side walls and a bottom wall formed by a surface of the base, the side walls being edges of directly adjacent interconnection elements of the plurality of interconnection elements.
In accordance with one or more particular aspects of the disclosure, the method may further include etching a monolithic conductive material having planar first and second surfaces to form the conductive structure, including etching the monolithic conductive material to form the plurality of interconnection elements.
According to an aspect of the disclosure, a method of making a microelectronic package includes bonding a conductive structure to a carrier so that the conductive structure overlies a rear surface of a microelectronic element disposed on the carrier and an exposed top surface of the carrier, the conductive structure being a monolithic structure having a base and a plurality of interconnections extending continuously away from the base toward the carrier, the plurality of interconnections having free ends overlying the carrier, wherein the microelectronic element is positioned between at least two adjacent interconnections of the plurality of interconnections; encapsulating the plurality of interconnections and the microelectronic element with an encapsulant; removing the carrier to expose the free ends of the interconnections and bond pads of the microelectronic element; conductively connecting the free ends of the interconnections and bond pads of the microelectronic element with terminals of the microelectronic package; and patterning the conductive structure to form external contacts, at least some of the external contacts overlying the microelectronic element.
In accordance with one or more particular aspects of the disclosure, patterning the conductive structure occurs after the encapsulating.
In accordance with one or more particular aspects of the disclosure, positioning the conductive structure includes positioning ends of the plurality of interconnections in contact with the carrier, such that removal of the carrier exposes the ends.
In accordance with one or more particular aspects of the disclosure, the conductive structure is substantially planar.
In accordance with one or more particular aspects of the disclosure, patterning the conductive structure further includes patterning the conductive structure to create conductive connections overlying the microelectronic element.
In accordance with one or more particular aspects of the disclosure, the method further includes etching a solder mask to expose surfaces of the external contacts and depositing solder masses on exposed portions of the external contacts.
In accordance with one or more particular aspects of the disclosure, the method may further include etching a monolithic conductive material having planar first and second surfaces to form the monolithic structure, including etching the monolithic conductive material to form the plurality of interconnection elements.
According to an aspect of the disclosure, a microelectronic package includes a microelectronic element, a redistribution structure, a plurality of back side conductive components, and an encapsulant. The microelectronic element may have bond pads at a front surface and an opposed rear surface. The redistribution structure may be configured to conductively connect bond pads of the microelectronic element with terminals of the microelectronic package. The plurality of back side conductive connections may be etched monolithic structures, at least some of the back side conductive connections including a back side routing layer and a plurality of interconnection elements extending continuously away from the back side routing layer. At least one of the plurality of back side conductive connections may include a back side routing layer overlying the rear surface of the microelectronic element. The encapsulant may encapsulate the plurality of interconnection elements and the microelectronic element so as to form an interconnection surface, the interconnection surface may be a planar surface along which the bond pads, ends of the interconnection elements, and surface of the encapsulant extend. The interconnection surface may be adjacent the redistribution structure.
In accordance with one or more particular aspects of the disclosure, a height of the microelectronic element may be less than the height of the plurality of interconnection elements.
In accordance with one or more particular aspects of the disclosure, the redistribution structure includes contacts disposed at a first surface, the bond pads of the microelectronic element joined to the conductive components of the first surface of the redistribution structure.
The accompanying drawings show exemplary embodiments in accordance with one or more aspects of exemplary assemblies and methods. However, these drawings should not be considered as limiting the scope of the claims, but provide examples that are for explanation and understanding only.
As illustrated in
As used in this disclosure, terms such as “upper,” “lower,” “top,” “bottom,” “above,” “below,” and similar terms denoting directions, refer to the frame of reference of the components themselves, rather than to the gravitational frame of reference. With the parts oriented in the gravitational frame of reference in the directions shown in the figures, with the top of drawing being up and the bottom of the drawing being down in the gravitational frame of reference, the top surface of the microelectronic element is, indeed, above the bottom surface of the microelectronic element in the gravitational frame of reference. However, when the parts are turned over, with the top of the drawing facing downwardly in the gravitational frame of reference, the top surface of the microelectronic element is below the bottom surface of the microelectronic element in the gravitational frame of reference.
With reference to a dielectric region or a dielectric structure of a component, e.g., circuit structure, interposer, microelectronic element, capacitor, voltage regulator, circuit panel, substrate, etc., As used in this disclosure, a statement that an electrically conductive element is “at” a surface of the carrier, dielectric region, or other component indicates that, when the surface is not covered or assembled with any other element, the electrically conductive element is available for contact with a theoretical point moving in a direction perpendicular to that surface of the dielectric region from outside the dielectric region or component. Thus, a terminal or other conductive element which is at a surface of a dielectric region may project from such surface; may be flush with such surface; or may be recessed relative to such surface in a hole or depression in the dielectric region.
In
The plurality of back side conductive components 110 may be formed from continuous unitary structures (
A manufacturing process that incorporates back side conductive components 110 that are integrally formed from a pre-processed unitary structure, as opposed to being formed by plating conductive vias or the like, allows for improvements over known assemblies, including a reduction in the overall cost of the assembly, simplified fabrication, improvements on package warpage, small form factor, and various other improvements.
The microelectronic element 120 can be a semiconductor chip having a plurality of bond pads 122 at its front surface 124 and an edge surface 126 extending away from the front surface 124 of the microelectronic element 120. Each microelectronic element 120 also includes a rear surface 128 opposite from its front surface 124. In one example, the microelectronic element 120 may be a semiconductor chip having one or more memory storage arrays, which may include a particular memory type such as nonvolatile memory. Nonvolatile memory can be implemented in a variety of technologies some of which include memory cells that incorporate floating gates, such as, for example, flash memory, and others which include memory cells which operate based on magnetic polarities. Flash memory chips are currently in widespread use as solid state storage as an alternative to magnetic fixed disk drives for computing and mobile devices. Flash memory chips are also commonly used in portable and readily interchangeable memory drives and cards, such as Universal Serial Bus (USB) memory drives, and memory cards such as Secure Digital or SD cards, microSD cards (trademarks or registered trademarks of SD-3C), compact flash or CF card and the like. Flash memory chips typically have NAND or NOR flash type devices therein; NAND type devices are more common. Other examples of semiconductor chips are one or more DRAM, NOR, microprocessor, controller die, etc. or combinations thereof. Each semiconductor chip may be implemented in one of various semiconductor materials such as silicon, germanium, and gallium arsenide or one or more other Group III-V semiconductor compounds or Group II-VI semiconductor compounds, etc.
A material can be provided within the assembly 100 between the microelectronic element and the back side routing layer 112. In one example, a material capable of conducting heat away from the microelectronic element 120 may be used. In one example, the material is thermal interface material (“TIM”), but in other examples, a non-thermal interface material may alternatively or additionally be used. As shown, a thermal interface material 130 overlies the rear surface 128 of the microelectronic element 120. The thermal interface material 130 can also be used to bond the interior surface 111 of the back side routing layer 112 to the microelectronic element 120. Exemplary TIMs are those that exist in semisolid, gel-like (grease-like) state throughout the range of expected operating temperatures (e.g. 0 degrees Celsius to 200 degrees Celsius for some assemblies) or at least when the temperatures are high to make die cooling particularly desirable (20 degrees Celsius to 200 degrees Celsius for some assemblies). The thermal interface material 130 can fill the free space between microelectronic element 120 and the routing layer 112A of the backside conductive component 110. An exemplary TIM material is a thermal grease available from Arctic Silver, Inc. (having an office in California, USA); the grease's thermal conductivity is in the range of 1 W/mK.
The microelectronic element 120 and the interconnection elements 114 of the back side conductive components 110 may be encapsulated within an encapsulant 134. As shown, the back side routing layers 112 can overlie the top surface 136 of the encapsulant 134. Ends 116 of the interconnection elements 114 can be positioned adjacent the bottom surface 138 of the encapsulant 134. The encapsulant 134 can also extend adjacent the edge surfaces 126 of the microelectronic element 120, as well as the edge surfaces 132 of the thermal interface material 130.
In particular embodiments, the material forming the encapsulant 134 can be an epoxy-based polymer system with fillers, overmold, or potting compound. Such compound can provide stiffness to the overall assembly 100 to withstand internal differential thermal expansion between the assembly 100 and other components within the assembly. The compound may in some cases provide protection from shorting and moisture and/or water resistance. Such material can further help to provide a relatively rigid encapsulation which supports planarity of the overall assembly 100. The material of the encapsulant 134 may typically include a composition different from the composition of the dielectric layers of the redistribution structure 140.
The redistribution structure 140 can also be referred to as a “circuit structure” made of a plurality of dielectric layers and electrically conductive features thereon, as described generally in U.S. Provisional Application 62/159,136, the disclosure of which is incorporated by reference herein. The electrically conductive features may comprise a plurality of bumps at a first surface of the circuit structure facing the contacts of the dielectric element and joined thereto, a plurality of circuit structure contacts at a second surface opposite the first surface. The circuit structure may further include a plurality of traces, wherein the bumps and the circuit structure contacts are electrically coupled by the traces.
In one example, the redistribution structure 140 can comprise or can be made from a plurality of thin dielectric layers 142 stacked one atop another, and front contacts 144 at the front surface 146, rear contacts or terminals 148 at the rear surface 150, and conductive traces 152 electrically coupling the front contacts 144 with the terminals or rear contact 148 of the assembly 100. In one example, the redistribution structure 140 can have a maximum thickness T1 of less than 10 microns in a direction normal to the front surface 146 of the redistribution structure 140. In a particular example, the redistribution structure 140 can have a maximum thickness T1 of less than 30 microns in a direction normal to the front surface 146 of the redistribution structure 140.
The dielectric material of the dielectric layers 142 can be a material that can be deposited and patterned to form structures that support metallization thereon at a pitch of less than 5 microns, less than 2 microns, less than 1 micron, or at least as low as 0.2 microns. In one embodiment, each of the dielectric layers 142 can be planarized before depositing the next dielectric layer. In particular examples, the dielectric material can be deposited by chemical vapor deposition (“CVD”), spray coating, spin coating, roller coating, dipping, or the like.
The dielectric layers 142 may be made from various dielectric materials, such as, for example polymer base or a polyimide. In other examples, the dielectric layers may be composed of alternative dielectric materials, such as silicon dioxide and silicon nitride. In particular examples, the dielectric material can be a photosensitive polymer, e.g., benzocyclobutene (“BCB”) based material, or other photosensitive material. In particular examples, the dielectric material can be deposited by chemical vapor deposition (“CVD”), spray coating, spin coating, roller coating, slot die coating, dipping, or the like. In particular examples, a self-planarizing dielectric material can be deposited to form one or more of the dielectric layers, such material having a tendency to form a flattened or flat upper surface as compared to topography that may be present in features underlying the upper surface.
The electrically conductive features of the redistribution structure 140 can provide electrical interconnection between the microelectronic element 120 and components external to the assembly 100. The electrically conductive features of the redistribution structure 140 can also provide chip-to-chip electrical interconnectivity among other microelectronic elements (not shown) that may be present in the assembly 100. The front contacts 144 of the redistribution structure 140 can be configured for flip-chip connection with a plurality of bond pads 122 at the front surface of the microelectronic element 120 and overlie different portions of an area of the front surface 146 of the redistribution structure 140. Stated another way, the front contacts 144 can be configured to be joined with the corresponding bond pads 122, in a state in which the front contacts 144 of the redistribution structure are juxtaposed with, i.e., face the corresponding bond pads 122 of the microelectronic element 120.
The electrically conductive features including the bumps 162, front contacts 144, rear contacts 148, and the conductive traces 152 can be made of an electrically conductive material, for example, a metal such as copper, aluminum, nickel, gold, or the like. In one example, the bumps 162 can comprise an electrically conductive bond material such as solder, tin, indium, copper, gold, a eutectic composition or combination thereof, another joining material such as a conductive paste or a conductive adhesive, and/or an electrically conductive composition that includes a metal component such as metal particles or flakes and a polymeric component. Such bumps can be deposited onto the front contacts 180.
In a particular embodiment, the conductive bond material of the bumps 162 can include an electrically conductive matrix material such as described in U.S. patent application Ser. Nos. 13/155,719 and 13/158,797, the disclosures of which are hereby incorporated herein by reference. In a particular embodiment, the conductive bond material of the bumps 162 can have a similar structure or be formed in a manner as described therein. In some examples, suitable materials for the conductive bond material of the bumps 162 can include polymers filled with conductive material in particle form such as metal-filled polymers, including, for example, metal-filled epoxy, metal-filled thermosetting polymers, metal-filled thermoplastic polymers, or electrically conductive inks.
Alternatively, the bumps 162 can comprise posts or pins, stud bumps or bond via interconnects each formed of extruded wire, such bumps projecting to heights thereof from the second side 108 of the assembly 100, and can be joined with components external to the microelectronic assembly 100, such as the circuit board 160.
Interconnection elements may be provided on the back side of the microelectronic assembly 100. Bumps 164 may also be provided on opposed portion of the assembly overlying the top surface 136 of the encapsulant 134 and provide an electrical interconnection to a component external to the back side of the microelectronic assembly 100. As shown, a dielectric layer, for example, solder mask 166, may overlie the first side 106 of the back side conductive component 110. Openings 168 in the solder mask 166 expose at least a portion of the outer surfaces 113 of the routing layer 112 so as to provide conductive contacts. The bumps 164 may be disposed at the conductive contacts exposed portions of the outer surfaces 113 of the back side routing layers 112 to provide an external connection. The bumps 164 can also be electrically connected to the bumps 162 at the second side 108 of the microelectronic assembly 100 through the back side conductive component 110, including the back side routing layer 112 and interconnection elements 114, as well as the redistribution structure 140.
As in the previously-described embodiment, microelectronic assembly 200 can include a plurality of back side conductive components 210, each of which can further include an integrally formed back side routing layer 212 and interconnection elements 214. The back side conductive components 210 may also include a back side routing layer 212A alone, without the presence of one or more interconnection elements 214. An encapsulant 234 encapsulates the microelectronic element 220 and the interconnection elements 214. Exposed ends 216 of the interconnection elements 214 are electrically connected with the redistribution structure 240, and in particular front contacts 244 at the surface of the redistribution structure 240. The back side routing layers 212 overlie the top surface 236 of the encapsulant 234. The microelectronic assembly 200 can be electrically interconnected with components external to the assembly 200 at both the rear side 208 and front side 206 of the assembly 200 through the back side conductive components 210 and the respective connections 264 and 262. In one example, as shown, the assembly 200 is joined to a circuit board 260.
A method of fabricating a microelectronic assembly according to aspects of the disclosure will now be described relative to
A conductive structure 472 can be used to provide back side routing and interconnection elements. An example conductive structure 472, prior to being patterned, is illustrated in
The conductive structure 472 may be a monolithic structure that is patterned, such as by etching or other known means, to include a plurality of interconnection elements. Example interconnection elements 484 are illustrated in
The interconnection elements 484 may extend outwardly and away from the base of the conductive structure 472. An example base 480 can includes a first outer surface 479 that is planar (which is the same surface as the first surface 474 of the conductive material 472), an opposed second surface 481 that is parallel to the first outer surface 484, and an edge surface 487 that extends between the first and second surfaces 479, 481. A first end 483 of each of the interconnection elements 484 is disposed at the second surface 481 of the base 480 of the conductive structure 472. The interconnection elements 484 can include edge surfaces 485 that extend from the second surface 481 of the base to opposed second ends 486 of the respective interconnection element 484. As shown, the second ends 486 of the interconnection elements 484 are exposed. The spacing and number of interconnection elements 484 may vary based upon the number of desired connections. Six interconnection elements 484 are shown in this example, but a greater or fewer number of interconnection elements may also be utilized.
A plurality of recesses 478A-478G are formed between each of the interconnection elements 484 and can vary in width. Recess 478D is a central recess that includes a width W1 that is at least large enough to receive the width of a microelectronic element. The interconnection elements 484 disposed on either side of the recess 478D may be equally spaced apart from one another. However, any desired pitch can be achieved. In this example recesses 478B-C and 478E-F may have widths W2 that are equal to the widths W3 of recesses 478A and 478G. In other examples, the widths W2 and W3 may differ. For example, widths W2 may be less than the widths W3 and vice versa.
The boundary or edge of a recess can be defined by a sidewall edge of one of the interconnection elements 484. For example, the edges 485 of two adjacent interconnection elements 484 and a floor 477 defined by the second surface 481 of the base 480 form the boundaries of the recess, such as recess 478B. Peripheral recesses 478A and 478G will only have a single interconnection element 484 directly adjacent the recess, such that only one recess wall surface is present. The central recess 478D is the largest of the recesses and can be sized to receive one or more microelectronic elements therein.
The conductive structure 472 can be joined with the carrier 470 and the microelectronic element 420, as shown, for example, in
As seen in
In one example, the dielectric encapsulation can be formed by flowing an encapsulant into a mold onto the elements shown in
Thereafter, as seen in
A redistribution structure can be provided at the interconnection surface. The redistribution structure, such as, for example, the redistribution structure 440 shown in
In the example of forming the redistribution structure directly thereon, the process can be performed so as to form a plurality of dielectric layers 442 and electrically conductive features such as described above with reference to
The conductive structure 472 can be processed to form a plurality of back side conductive components. As shown, for example, in
A dielectric layer, such as a solder mask 490 may be provided over the back side routing layer 412 of the back side conductive component 410, as shown in
In the alternative example where the redistribution structure carrier is pre-formed, the front surfaces of the redistribution structure may be bonded to the exposed ends 486 of the interconnection elements 414 with an adhesive (not shown). In one embodiment, the adhesive may be or include one or more layers of epoxy, elastomer, polyimide or other polymeric material. In some cases, a material used as a conformal dielectric coating over one or more of the microelectronic elements may also function as an adhesive. In one embodiment, such conformal dielectric coating can be a polyxylylene material such as commonly referred to as “parylene”. Parylene can also be used as a die attach adhesive between adjacent microelectronic elements.
With reference to
The microelectronic element 520 and conductive component 572 can be encapsulated, as shown in
Turning now to
With reference to
The assemblies described above with reference to
In the exemplary system 1000 shown, the system can include a circuit panel, motherboard, or riser panel 1002 such as a flexible printed circuit board, and the circuit panel can include numerous conductors 1004, of which only one is depicted in
In a particular embodiment, the system 1000 can also include a processor such as the semiconductor chip 1008, such that each module or component 1006 can be configured to transfer a number N of data bits in parallel in a clock cycle, and the processor can be configured to transfer a number M of data bits in parallel in a clock cycle, M being greater than or equal to N. Additionally, other chip packages, such as chip packages 1008′ may be provided within the system, as well.
In the example depicted in
Modules or components 1006 and components 1008, 1010, and 1011 can be mounted in a common housing 1001, schematically depicted in broken lines, and can be electrically interconnected with one another as necessary to form the desired circuit. The housing 1001 is depicted as a portable housing of the type usable, for example, in a cellular telephone or personal digital assistant, and screen 1010 can be exposed at the surface of the housing. In embodiments where a structure 1006 includes a light-sensitive element such as an imaging chip, a lens 1011 or other optical device also can be provided for routing light to the structure. Again, the simplified system shown in
The incorporation of back side conductive components manufactured according to the disclosure herein into microelectronic assemblies can provide improvements over the art. Such assemblies allow for lower cost construction due to the materials needed and a small form factor. Additionally, for assemblies including a redistribution structure, the back side routing layer can counter-balance warpage caused by the redistribution structure. While certain examples were disclosed herein, it should be appreciated that back side routing layers can be further designed for antenna layout, electromagnetic interference shielding, three-dimensional connections, and heat dissipation.
Unless otherwise stated, the foregoing alternative examples are not mutually exclusive, but may be implemented in various combinations to achieve unique advantages. As these and other variations and combinations of the features discussed above can be utilized without departing from the subject matter defined by the claims, the foregoing description of the embodiments should be taken by way of illustration rather than by way of limitation of the subject matter defined by the claims. In addition, the provision of the examples described herein, as well as clauses phrased as “such as,” “including” and the like, should not be interpreted as limiting the subject matter of the claims to the specific examples; rather, the examples are intended to illustrate only one of many possible embodiments. Further, the same or similar reference numbers in different drawings can identify the same or similar elements.
The present application is a continuation of U.S. patent application Ser. No. 16/245,925, filed on Jan. 11, 2019 (now U.S. Pat. No. 11,031,362), which is a divisional of U.S. patent application Ser. No. 15/493,917, filed on Apr. 21, 2017, and issued as U.S. Pat. No. 10,181,447, the disclosures all of which are incorporated herein by reference.
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| 20210366857 A1 | Nov 2021 | US |
| Number | Date | Country | |
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| Parent | 15493917 | Apr 2017 | US |
| Child | 16245925 | US |
| Number | Date | Country | |
|---|---|---|---|
| Parent | 16245925 | Jan 2019 | US |
| Child | 17340469 | US |
